CY7C1011CV33
2-Mbit (128 K 16) Static RAM
2-Mbit (128 K 16) Static RAM
Features Functional Description
Temperature ranges The CY7C1011CV33 is a high performance complementary
metal oxide semiconductor (CMOS) static RAM organized as
Industrial: 40 C to 85 C
131,072 words by 16 bits. This device has an automatic power
Automotive-A: 40 C to 85 C
down feature that significantly reduces power consumption when
Automotive-E: 40 C to 125 C
deselected.
Pin and function compatible with CY7C1011BV33
To write to the device, take CE and Write Enable (WE) inputs
LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins
High speed
(I/O through I/O ), is written into the location specified on the
0 7
t = 10 ns (Industrial and Automotive-A)
AA
address pins (A through A ). If Byte High Enable (BHE) is
0 16
t = 12 ns (Automotive-E)
AA
LOW, then data from I/O pins (I/O through I/O ) is written into
8 15
Low active power
the location specified on the address pins (A through A ).
0 16
360 mW (max) (Industrial and Automotive-A)
To read from the device, take CE and OE LOW while forcing the
Write Enable (WE) HIGH. If BLE is LOW, then data from the
2.0 V data retention
memory location specified by the address pins appear on I/O to
0
Automatic power down when deselected
I/O . If Byte High Enable (BHE) is LOW, then data from memory
7
appears on I/O to I/O . For more information, see the Truth
8 15
Independent control of upper and lower bits
Table on page 11 for a complete description of Read and Write
Easy memory expansion with Chip Enable (CE) and Output modes.
Enable (OE) features
The input and output pins (I/O through I/O ) are placed in a
0 15
high impedance state when the device is deselected (CE HIGH),
Available in Pb-free 44-pin thin small outline package
the outputs are disabled (OE HIGH), the BHE and BLE are
(TSOP) II, 44-pin thin quad flat package (TQFP), and non
disabled (BHE, BLE HIGH), or during a write operation (CE LOW
Pb-free 48-ball very fine-pitch ball grid array (VFBGA)
and WE LOW).
packages
For a complete list of related documentation, click here.
Logic Block Diagram
INPUT BUFFER
A
0
A
1
A
2
A
3
128 K x 16
A
4
RAM Array I/O I/O
0 7
A
5
A
6
I/O I/O
8 15
A
7
A
8
COLUMN DECODER
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 38-05232 Rev. *P Revised July 24, 2015
ROW DECODER
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
SENSE AMPSCY7C1011CV33
Contents
Pin Configuration .............................................................3 Package Diagrams .......................................................... 13
Selection Guide ................................................................4 Acronyms ........................................................................15
Maximum Ratings .............................................................5 Document Conventions ................................................. 15
Operating Range ...............................................................5 Units of Measure ....................................................... 15
Electrical Characteristics .................................................5 Document History Page ................................................. 16
Capacitance ......................................................................6 Sales, Solutions, and Legal Information ...................... 18
Thermal Resistance ..........................................................6 Worldwide Sales and Design Support ....................... 18
AC Test Loads and Waveforms .......................................6 Products ....................................................................18
Switching Characteristics ................................................7 PSoC Solutions ...................................................... 18
Switching Waveforms ......................................................8 Cypress Developer Community ................................. 18
Truth Table ......................................................................11 Technical Support ..................................................... 18
Ordering Information ......................................................12
Ordering Code Definitions .........................................12
Document Number: 38-05232 Rev. *P Page 2 of 18