CY7C1011DV33 2-Mbit (128 K 16) Static RAM 2-Mbit (128 K 16) Static RAM Features Functional Description 1 Pin-and function-compatible with CY7C1011CV33 The CY7C1011DV33 is a high-performance CMOS Static RAM organized as 128 K words by 16 bits. High speed Writing to the device is accomplished by taking Chip Enable (CE) t = 10 ns AA and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is Low active power LOW, then data from I/O pins (I/O through I/O ), is written into 0 7 the location specified on the address pins (A through A ). If I = 90 mA 10 ns (Industrial) 0 16 CC Byte High Enable (BHE) is LOW, then data from I/O pins (I/O 8 Low CMOS standby power through I/O ) is written into the location specified on the address 15 I = 10 mA SB2 pins (A through A ). 0 16 Data Retention at 2.0 V Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Automatic power-down when deselected Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will Independent control of upper and lower bits appear on I/O to I/O . If Byte High Enable (BHE) is LOW, then 0 7 Easy memory expansion with CE and OE features data from memory will appear on I/O to I/O . See the truth table 8 15 at the back of this data sheet for a complete description of read Available in Pb-free 44-pin TSOP II, and 48-ball VFBGA and write modes. The input/output pins (I/O through I/O ) are placed in a 0 15 high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1011DV33 is available in standard Pb-free 44-pin TSOP II with center power and ground pinout, as well as 48-ball very fine-pitch ball grid array (VFBGA) packages. Logic Block Diagram INPUT BUFFER A 0 A 1 A 2 I/O I/O A 0 7 3 A 4 128K X 16 A I/O I/O 5 8 15 A 6 A 7 A 8 COLUMN DECODER BHE WE CE OE BLE Note 1. For guidelines on SRAM system design, please refer to the System Design Guidelines Cypress application note, available on the internet at www.cypress.com Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05609 Rev. *F Revised January 8, 2013 ROW DECODER A 9 A 10 A 11 A 12 A 13 A 14 A15 A 16 SENSE AMPSCY7C1011DV33 Contents Selection Guide ................................................................3 Write Cycle No. 3 (WE Controlled, Pin Configurations ...........................................................3 OE HIGH During Write) ...................................................... 9 Maximum Ratings .............................................................4 Write Cycle No. 4 (WE Controlled, OE LOW) ............. 9 Operating Range ...............................................................4 Truth Table ...................................................................... 10 DC Electrical Characteristics ..........................................4 Ordering Information ...................................................... 10 Capacitance ......................................................................4 Ordering Code Definitions ......................................... 10 Thermal Resistance ..........................................................4 Package Diagrams .......................................................... 11 AC Test Loads and Waveforms .......................................5 Acronyms ........................................................................12 AC Switching Characteristics .........................................5 Document Conventions ................................................. 12 Data Retention Characteristics .......................................6 Units of Measure ....................................................... 12 Data Retention Waveform ................................................6 Document History ........................................................... 13 Switching Waveforms ......................................................7 Sales, Solutions, and Legal Information ...................... 14 Read Cycle No. 1 ........................................................7 Worldwide Sales and Design Support ....................... 14 Read Cycle No. 2 (OE Controlled) ..............................7 Products ....................................................................14 Write Cycle No. 1 (CE Controlled) ...............................8 PSoC Solutions ......................................................... 14 Document Number: 38-05609 Rev. *F Page 2 of 14