CY7C1012AV33
512 K 24 Static RAM
512 K 24 Static RAM
Features Functional Description
High speed The CY7C1012AV33 is a high-performance CMOS static RAM
organized as 512 K words by 24 bits. Each data byte is
t = 8 ns
AA
separately controlled by the individual chip selects (CE , CE ,
0 1
Low active power
CE ). CE controls the data on the I/O I/O , while CE controls
2 0 0 7 1
1080 mW (max)
the data on I/O I/O , and CE controls the data on the data
8 15 2
pins I/O I/O . This device has an automatic power-down
16 23
Operating voltages of 3.3 0.3 V
feature that significantly reduces power consumption when
2.0 V data retention deselected.
Writing the data bytes into the SRAM is accomplished when the
Automatic power-down when deselected
chip select controlling that byte is LOW and the write enable input
TTL-compatible inputs and outputs
(WE) input is LOW. Data on the respective input/output (I/O) pins
is then written into the location specified on the address pins
Easy memory expansion with CE , CE and CE features
0 1 2
(A A ). Asserting all of the chip selects LOW and write enable
0 18
Available in non Pb-free 119 ball PBGA. LOW will write all 24 bits of data into the SRAM. Output enable
(OE) is ignored while in WRITE mode.
Data bytes can also be individually read from the device.
Reading a byte is accomplished when the chip select controlling
that byte is LOW and write enable (WE) HIGH while output
enable (OE) remains LOW. Under these conditions, the contents
of the memory location specified on the address pins will appear
on the specified data input/output (I/O) pins. Asserting all the chip
selects LOW will read all 24 bits of data from the SRAM.
The 24 I/O pins (I/O I/O ) are placed in a high-impedance
0 23
state when all the chip selects are HIGH or when the output
enable (OE) is HIGH during a READ mode. For further details,
refer to the truth table of this data sheet.
The CY7C1012AV33 is available in a standard 119-ball PBGA.
For a complete list of related documentation, click here.
Functional Block Diagram
INPUT BUFFER
A
0
A
1
A
2 I/O I/O
0 7
A
3
512K x 24
A
4
ARRAY I/O I/O
8 15
A
5
A
6
I/O I/O
16 23
A
7
A
8
A
9
CE , CE , CE
0 1 2
COLUMN
WE
CONTROL LOGIC
DECODER
OE
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 38-05254 Rev. *J Revised November 18, 2014
ROW DECODER
A
10
A11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
SENSE AMPSCY7C1012AV33
Contents
Selection Guide ................................................................3 Package Diagram ............................................................ 11
Pin Configurations ...........................................................3 Acronyms ........................................................................12
Maximum Ratings .............................................................4 Document Conventions ................................................. 12
Operating Range ...............................................................4 Units of Measure ....................................................... 12
DC Electrical Characteristics ..........................................4 Document History Page ................................................. 13
Capacitance ......................................................................5 Sales, Solutions, and Legal Information ...................... 14
AC Test Loads and Waveforms .......................................5 Worldwide Sales and Design Support ....................... 14
AC Switching Characteristics .........................................6 Products ....................................................................14
Switching Waveforms ......................................................7 PSoC Solutions ...................................................... 14
Truth Table ........................................................................9 Cypress Developer Community ................................. 14
Ordering Information ......................................................10 Technical Support ..................................................... 14
Ordering Code Definitions .........................................10
Document Number: 38-05254 Rev. *J Page 2 of 14