CY7C1012DV33 12-Mbit (512 K 24) Static RAM 12-Mbit (512 K 24) Static RAM Features Functional Description High speed The CY7C1012DV33 is a high performance CMOS static RAM organized as 512K words by 24 bits. Each data byte is separately t = 10 ns AA controlled by the individual chip selects (CE , CE , and CE ). 1 2 3 Low active power CE controls the data on the I/O I/O , while CE controls the 1 0 7 2 I = 175 mA at 10 ns data on I/O I/O , and CE controls the data on the data pins CC 8 15 3 I/O I/O . This device has an automatic power down feature 16 23 Low CMOS standby power that significantly reduces power consumption when deselected. I = 25 mA SB2 Writing the data bytes into the SRAM is accomplished when the Operating voltages of 3.3 0.3 V chip select controlling that byte is LOW and the write enable input (WE) input is LOW. Data on the respective input and output (I/O) 2.0 V data retention pins is then written into the location specified on the address pins Automatic power down when deselected (A A ). Asserting all of the chip selects LOW and write enable 0 18 LOW writes all 24 bits of data into the SRAM. Output enable (OE) TTL compatible inputs and outputs is ignored while in WRITE mode. Available in Pb-free standard 119-ball PBGA Data bytes are also individually read from the device. Reading a byte is accomplished when the chip select controlling that byte is LOW and write enable (WE) HIGH, while output enable (OE) remains LOW. Under these conditions, the contents of the memory location specified on the address pins appear on the specified data input and output (I/O) pins. Asserting all the chip selects LOW reads all 24 bits of data from the SRAM. The 24 I/O pins (I/O I/O ) are placed in a high impedance state 0 23 when all the chip selects are HIGH or when the output enable (OE) is HIGH during a READ mode. For more information, see the Truth Table on page 10. For a complete list of related documentation, click here. Logic Block Diagram INPUT BUFFER I/O I/O 0 7 512 K x 24 ARRAY I/O I/O A 8 15 (9:0) I/O I/O 16 23 CE , CE , CE 1 2 3 COLUMN DECODER WE CONTROL LOGIC OE A (18:10) Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05610 Rev. *G Revised November 20, 2014 ROW DECODER SENSE AMPSCY7C1012DV33 Contents Selection Guide ................................................................3 Ordering Information ...................................................... 11 Pin Configuration .............................................................3 Ordering Code Definitions ......................................... 11 Maximum Ratings .............................................................4 Package Diagram ............................................................ 12 Operating Range ...............................................................4 Acronyms ........................................................................13 DC Electrical Characteristics ..........................................4 Document Conventions ................................................. 13 Capacitance ......................................................................5 Units of Measure ....................................................... 13 Thermal Resistance ..........................................................5 Document History Page ................................................. 14 AC Test Loads and Waveforms .......................................5 Sales, Solutions, and Legal Information ...................... 15 AC Switching Characteristics .........................................6 Worldwide Sales and Design Support ....................... 15 Data Retention Characteristics .......................................7 Products ....................................................................15 Data Retention Waveform ................................................7 PSoC Solutions ......................................................... 15 Switching Waveforms ......................................................7 Truth Table ......................................................................10 Document Number: 38-05610 Rev. *G Page 2 of 15