CY7C1018DV33 CY7C1019DV33 1-Mbit (128 K 8) Static RAM 1-Mbit (128 K 8) Static RAM Features Functional Description Pin- and function-compatible with CY7C1018CV33 and The CY7C1018DV33/CY7C1019DV33 is a high-performance CY7C1019CV33 CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable High speed (CE), an active LOW Output Enable (OE), and three-state t = 10 ns AA drivers. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Low Active Power Writing to the device is accomplished by taking Chip Enable (CE) I = 60 mA 10 ns CC and Write Enable (WE) inputs LOW. Data on the eight I/O pins Low CMOS Standby Power (I/O through I/O ) is then written into the location specified on 0 7 I = 3 mA SB2 the address pins (A through A ). 0 16 2.0 V Data retention Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable Automatic power-down when deselected (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. CMOS for optimum speed/power The eight input/output pins (I/O through I/O ) are placed in a 0 7 Center power/ground pinout high-impedance state when the device is deselected (CE HIGH), Easy memory expansion with CE and OE options the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). Available in Pb-free 32-pin 400-Mil wide Molded SOJ, 32-pin The CY7C1018DV33/CY7C1019DV33 are available in Pb-free TSOP II and 48-ball VFBGA packages 32-pin 400-Mil wide Molded SOJ, 32-pin TSOP II and 48-ball VFBGA packages. For a complete list of related documentation, click here. Logic Block Diagram I/O 0 INPUTBUFFER I/O 1 A 0 A 1 I/O 2 A 2 A 3 128K 8 I/O A 4 3 ARRAY A 5 A I/O 6 4 A 7 A 8 I/O 5 CE I/O POWER 6 COLUMN WE DOWN DECODER I/O 7 OE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05481 Rev. *J Revised May 26, 2015 ROW DECODER A 9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 SENSE AMPSCY7C1018DV33 CY7C1019DV33 Contents Selection Guide ................................................................3 Ordering Information ...................................................... 12 Pin Configurations ...........................................................3 Ordering Code Definitions ......................................... 12 Maximum Ratings .............................................................4 Package Diagrams .......................................................... 13 Operating Range ...............................................................4 Acronyms ........................................................................17 Electrical Characteristics .................................................4 Document Conventions ................................................. 17 Capacitance ......................................................................5 Units of Measure ....................................................... 17 Thermal Resistance ..........................................................5 Document History Page ................................................. 18 AC Test Loads and Waveforms .......................................5 Sales, Solutions, and Legal Information ...................... 20 Data Retention Characteristics .......................................6 Worldwide Sales and Design Support ....................... 20 Data Retention Waveform ................................................6 Products ....................................................................20 Switching Characteristics ................................................7 PSoC Solutions ...................................................... 20 Switching Waveforms ......................................................8 Cypress Developer Community ................................. 20 Truth Table ......................................................................11 Technical Support ..................................................... 20 Document Number: 38-05481 Rev. *J Page 2 of 20