CY7C1019DV33 1-Mbit (128 K 8) Static RAM 1-Mbit (128 K 8) Static RAM Features Functional Description Pin- and function-compatible with CY7C1019CV33 The CY7C1019DV33 is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion High speed is provided by an active LOW Chip Enable (CE), an active LOW t = 10 ns AA Output Enable (OE), and three-state drivers. This device has an automatic power-down feature that significantly reduces power Low Active Power consumption when deselected. I = 60 mA 10 ns CC Writing to the device is accomplished by taking Chip Enable (CE) Low CMOS Standby Power and Write Enable (WE) inputs LOW. Data on the eight I/O pins I = 3 mA SB2 (I/O through I/O ) is then written into the location specified on 0 7 the address pins (A through A ). 0 16 2.0 V Data retention Reading from the device is accomplished by taking Chip Enable Automatic power-down when deselected (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory CMOS for optimum speed/power location specified by the address pins will appear on the I/O pins. Center power/ground pinout The eight input/output pins (I/O through I/O ) are placed in a 0 7 Easy memory expansion with CE and OE options high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation Available in Pb-free 32-pin 400-Mil wide Molded SOJ, 32-pin (CE LOW, and WE LOW). TSOP II and 48-ball VFBGA packages The CY7C1019DV33 is available in Pb-free 32-pin 400-Mil wide Molded SOJ, 32-pin TSOP II and 48-ball VFBGA packages. Logic Block Diagram I/O 0 INPUTBUFFER I/O 1 A 0 A 1 I/O 2 A 2 A 3 128K 8 I/O A 4 3 ARRAY A 5 A I/O 6 4 A 7 A 8 I/O 5 CE I/O POWER 6 COLUMN WE DOWN DECODER I/O 7 OE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05481 Rev. *F Revised October 20, 2011 + Feedback ROW DECODER A 9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 SENSE AMPSCY7C1019DV33 Contents Selection Guide ................................................................3 Ordering Information ...................................................... 11 Pin Configurations ...........................................................3 Ordering Code Definitions ......................................... 11 Maximum Ratings .............................................................4 Package Diagrams .......................................................... 12 Operating Range ...............................................................4 Acronyms ........................................................................14 Electrical Characteristics .................................................4 Document Conventions ................................................. 14 Capacitance ......................................................................5 Units of Measure ....................................................... 14 Thermal Resistance ..........................................................5 Document History Page ................................................. 15 AC Test Loads and Waveforms .......................................5 Sales, Solutions, and Legal Information ...................... 16 Switching Characteristics ................................................6 Worldwide Sales and Design Support ....................... 16 Data Retention Characteristics .......................................7 Products ....................................................................16 Data Retention Waveform ................................................7 PSoC Solutions ......................................................... 16 Switching Waveforms ......................................................7 Truth Table ......................................................................10 Document Number: 38-05481 Rev. *F Page 2 of 16 + Feedback