CY7C1020D 512-Kbit (32 K 16) Static RAM 512-Kbit (32 K 16) Static RAM consumption when deselected.The input and output pins Features (IO through IO ) are placed in a high-impedance state when: 0 15 Pin- and function-compatible with CY7C1020B Deselected (CE HIGH) High speed Outputs are disabled (OE HIGH) t = 10 ns AA BHE and BLE are disabled (BHE, BLE HIGH) Low active power When the write operation is active (CE LOW, and WE LOW) I = 80 mA 10ns CC Write to the device by taking Chip Enable (CE) and Write Enable Low complementary metal oxide semiconductor (CMOS) (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data standby power from IO pins (IO through IO ), is written into the location 0 7 I = 3 mA SB2 specified on the address pins (A through A ). If Byte High 0 14 2.0 V data retention Enable (BHE) is LOW, then data from IO pins (IO through IO ) 8 15 is written into the location specified on the address pins (A 0 Automatic power-down when deselected through A ). 14 CMOS for optimum speed/power Reading from the device by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Independent control of upper and lower bits Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on IO to IO . If Available in Pb-free 44-pin 400-Mil wide Molded SOJ and 0 7 Byte High Enable (BHE) is LOW, then data from memory 44-pin thin small outline package (TSOP) II packages appears on IO to IO . See the Truth Table on page 11 for a 8 15 complete description of read and write modes. Functional Description The CY7C1020D device is suitable for interfacing with 1 The CY7C1020D is a high-performance CMOS static RAM processors that have TTL I/P levels. It is not suitable for organized as 32,768 words by 16 bits. This device has an processors that require CMOS I/P levels. Please see Electrical automatic power-down feature that significantly reduces power Characteristics on page 4 for more details and suggested alternatives. Logic Block Diagram DATA IN DRIVERS A 7 A 6 A 5 32K x 16 A 4 IO IO 0 7 RAM Array A 3 A IO IO 2 8 15 A 1 A 0 COLUMN DECODER BHE WE CE OE BLE Note 1. For guidelines on SRAM system design, please refer to the System Design Guidelines Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05463 Rev. *H Revised June 19, 2013 ROW DECODER A 8 A 9 A 10 A 11 A 12 A 13 A 14 SENSE AMPSCY7C1020D Contents Pin Configurations ...........................................................3 Ordering Information ...................................................... 12 Selection Guide ................................................................3 Ordering Code Definitions ......................................... 12 Maximum Ratings .............................................................4 Package Diagrams .......................................................... 13 Operating Range ...............................................................4 Acronyms ........................................................................15 Electrical Characteristics .................................................4 Document Conventions ................................................. 15 Capacitance ......................................................................5 Units of Measure ....................................................... 15 Thermal Resistance ..........................................................5 Document History Page ................................................. 16 AC Test Loads and Waveforms .......................................5 Sales, Solutions, and Legal Information ...................... 17 Data Retention Characteristics .......................................6 Worldwide Sales and Design Support ....................... 17 Data Retention Waveform ................................................6 Products ....................................................................17 Switching Characteristics ................................................7 PSoC Solutions ...................................................... 17 Switching Waveforms ......................................................8 Cypress Developer Community ................................. 17 Truth Table ......................................................................11 Technical Support ..................................................... 17 Document Number: 38-05463 Rev. *H Page 2 of 17