CY7C1020DV33 512 K (32 K x 16) Static RAM Writing to the device is accomplished by taking chip enable Features (CE) and write enable (WE) inputs LOW. If byte low enable (BLE) is LOW, then data from I/O pins (I/O through I/O ), is Pin-and function-compatible with CY7C1020CV33 0 7 written into the location specified on the address pins (A 0 High speed through A ). If byte high enable (BHE) is LOW, then data from 14 t = 10 ns I/O pins (I/O through I/O ) is written into the location AA 8 15 specified on the address pins (A through A ). 0 14 Low active power Reading from the device is accomplished by taking chip I = 60 mA 10 ns CC enable (CE) and output enable (OE) LOW while forcing the Low CMOS standby power write enable (WE) HIGH. If byte low enable (BLE) is LOW, then I = 3 mA data from the memory location specified by the address pins SB2 will appear on I/O to I/O . If byte high enable (BHE) is LOW, 0 7 2.0 V Data retention then data from memory will appear on I/O to I/O . See the 8 15 Automatic power-down when deselected truth table at the back of this data sheet for a complete description of read and write modes. CMOS for optimum speed/power The input/output pins (I/O through I/O ) are placed in a 0 15 Independent control of upper and lower bits high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE Available in Pb-free 44-pin 400-Mil wide Molded SOJ and are disabled (BHE, BLE HIGH), or during a write operation (CE 44-pin TSOP II packages LOW, and WE LOW). Functional Description The CY7C1020DV33 is available in Pb-free 44-pin 400-Mil wide Molded SOJ and 44-pin TSOP II packages. The CY7C1020DV33 is a high-performance CMOS static For a complete list of related documentation, click here. RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. 1 Logic Block Diagram Pin Configuration SOJ/TSOP II DATA IN DRIVERS Top View A NC 1 44 5 A A 2 43 3 6 A A 3 42 7 2 A 7 A 4 OE 41 A 1 6 A 5 A 0 40 BHE 5 32K x 16 6 39 A CE BLE 4 I/O I/O 0 7 RAM Array I/O 7 38 I/O A 0 15 3 I/O 8 37 I/O A I/O I/O 1 14 2 8 15 I/O 9 I/O 2 36 A 13 1 I/O I/O 10 35 3 12 A 0 V 11 V 34 CC SS V SS 12 33 V CC I/O 4 13 32 I/O 11 I/O I/O 5 14 31 10 COLUMN DECODER I/O I/O 15 30 6 9 I/O 16 29 I/O 7 8 BHE 17 28 WE NC WE A 18 27 A 4 8 CE A 26 A 14 19 9 OE A 13 20 25 A 10 A BLE 12 21 24 A 11 NC 22 23 NC Notes 1. NC pins are not connected on the die. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05461 Rev. *I Revised November 19, 2014 ROW DECODER A 8 A 9 A 10 A 11 A 12 A 13 A 14 SENSE AMPSCY7C1020DV33 Selection Guide 10 (Industrial) Unit Maximum access time 10 ns Maximum operating current 60 mA Maximum CMOS standby current 3 mA 2 DC input voltage ............................... 0.5 V to V + 0.5 V Maximum Ratings CC Current into outputs (LOW) ......................................... 20 mA (Above which the useful life may be impaired. For user guide- Static discharge voltage........................................... > 2001 V lines, not tested.) (per MIL-STD-883, Method 3015) Storage temperature ................................ 65 C to +150 C Latch-up current ..................................................... > 200 mA Ambient temperature with power applied ........................................... 55 C to +125 C Operating Range 2 Supply voltage on V to Relative GND ...0.5 V to +4.6 V CC Ambient Range V Speed DC voltage applied to outputs CC Temperature 2 in High-Z State .................................. 0.5 V to V + 0.5 V CC Industrial 40 C to +85 C 3.3 V 0.3 V 10 ns Electrical Characteristics Over the Operating Range 10 (Industrial) Parameter Description Test Conditions Unit Min. Max. V Output HIGH voltage V = Min., I = 4.0 mA 2.4 V OH CC OH V Output LOW voltage V = Min., I = 8.0 mA 0.4 V OL CC OL V Input HIGH voltage 2.0 V + 0.3 V IH CC 2 V Input LOW voltage 0.3 0.8 V IL I Input Load current GND < V < V 1+1 A IX I CC I Output leakage current GND < V < V , Output Disabled 1+1 A OZ I CC I V operating V = Max., 100 MHz 60 mA CC CC CC supply current I = 0 mA, OUT 83 MHz 55 mA f = f = 1/t MAX RC 66 MHz 45 mA 40 MHz 30 mA I Automatic CE Power-down Max. V , CE > V 10 mA SB1 CC IH CurrentTTL Inputs V > V or V < V , f = f IN IH IN IL MAX I Automatic CE Power-down Max. V , CE > V 0.3 V, 3mA SB2 CC CC CurrentCMOS Inputs V > V 0.3 V, or V < 0.3 V, f = 0 IN CC IN Notes 2. V (min.) = 2.0 V and V (max) = V + 1 V for pulse durations of less than 5 ns. IL IH CC Document Number: 38-05461 Rev. *I Page 2 of 13