CY7C1021BNV33 64K 16 Static RAM 64K 16 Static RAM Features Functional Description 1 3.3 V operation (3.0 V3.6 V) The CY7C1021BNV33 is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an High speed automatic power-down feature that significantly reduces power t = 15 ns AA consumption when deselected. CMOS for optimum speed/power Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is Low Active Power LOW, then data from I/O pins (I/O through I/O ), is written into 0 7 576 mW (max) the location specified on the address pins (A through A ). If 0 15 Byte High Enable (BHE) is LOW, then data from I/O pins (I/O Low CMOS Standby Power 8 through I/O ) is written into the location specified on the address 15 1.80 mW (max) pins (A through A ). 0 15 Automatic power-down when deselected Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Independent control of upper and lower bits Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data Available in 44-pin TSOP II and 48-ball Mini BGA package from the memory location specified by the address pins will appear on I/O to I/O . If Byte High Enable (BHE) is LOW, then 0 7 data from memory will appear on I/O to I/O . See the truth table 8 15 at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O through I/O ) are placed in a 0 15 high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1021BNV33 is available in standard 44-pin TSOP Type II and 48-ball mini BGA packages. For a complete list of related documentation, click here. Note 1. For guidelines on SRAM system design, please refer to the System Design Guidelines Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-06433 Rev. *G Revised December 13, 2017CY7C1021BNV33 Logic Block Diagram DATA IN DRIVERS A 7 A 6 A 64K x 16 5 A 4 RAM Array I/O I/O 0 7 A 3 A I/O I/O 2 8 15 A 1 A 0 COLUMN DECODER BHE WE CE OE BLE Selection Guide -15 Maximum Access Time (ns) 15 Maximum Operating Current (mA) 160 Maximum CMOS Standby Current (mA) 0.5 Document Number: 001-06433 Rev. *G Page 2 of 17 ROW DECODER A 8 A 9 A 10 A 11 A 12 A 13 A 14 A 15 SENSE AMPS