Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY7C1021CV33 Automotive 1-Mbit (64 K 16) Static RAM 1-Mbit (64 K 16) Static RAM Features Functional Description Temperature ranges The CY7C1021CV33 is a high performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an Automotive-A: 40 C to 85 C automatic power down feature that significantly reduces power Automotive-E: 40 C to 125 C consumption when deselected. Pin and function compatible with CY7C1021CV33 Writing to the device is accomplished by taking Chip Enable (CE) High speed and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is 1 LOW, then data from I/O pins (I/O through I/O ) , is written into t = 10 ns (Automotive-A) 1 8 AA the location specified on the address pins (A through A ). If 0 15 t = 12 ns (Automotive-E) AA Byte High Enable (BHE) is LOW, then data from I/O pins (I/O 9 1 CMOS for optimum speed and power through I/O ) is written into the location specified on the 16 address pins (A through A ). 0 15 Low active power: 325 mW (max) Reading from the device is accomplished by taking Chip Enable Automatic power down when deselected (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data Independent control of upper and lower bits from the memory location specified by the address pins appear 1 Available in Pb-free and non Pb-free 44-pin 400 Mil SOJ, 44-pin on I/O to I/O . If Byte High Enable (BHE) is LOW, then data 1 8 1 TSOP II, and 48-ball FBGA packages from memory appears on I/O to I/O . For more information, 9 16 see the Truth Table on page 11 for a complete description of Read and Write modes. The input and output pins (I/O through I/O ) are placed in a 1 16 high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). For a complete list of related documentation, click here. Logic Block Diagram DATA IN DRIVERS A 7 A 6 A 5 64K x 16 A 4 I/O I/O 1 0 7 RAM Array A 3 A I/O I/O 1 2 8 15 A 1 A 0 COLUMN DECODER BHE WE CE OE BLE Note 1. I/O I/O for SOJ/TSOP and I/O I/O for BGA packages. 1 16 0 15 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05132 Rev. *Q Revised December 2, 2014 ROW DECODER A 8 A 9 A 10 A 11 A 12 A 13 A 14 A 15 SENSE AMPS