CY7C1021CV33 1-Mbit (64 K 16) Static RAM 1-Mbit (64 K 16) Static RAM Features Functional Description Temperature ranges The CY7C1021CV33 is a high performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an Automotive-A: 40 C to 85 C automatic power down feature that significantly reduces power Automotive-E: 40 C to 125 C consumption when deselected. Pin and function compatible with CY7C1021CV33 Writing to the device is accomplished by taking Chip Enable (CE) High speed and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O through I/O ), is written into t = 10 ns (Automotive-A) 1 8 AA the location specified on the address pins (A through A ). If 0 15 t = 12 ns (Automotive-E) AA Byte High Enable (BHE) is LOW, then data from I/O pins (I/O 9 CMOS for optimum speed and power through I/O ) is written into the location specified on the address 16 pins (A through A ). 0 15 Low active power: 325 mW (max) Reading from the device is accomplished by taking Chip Enable Automatic power down when deselected (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data Independent control of upper and lower bits from the memory location specified by the address pins appear Available in Pb-free and non Pb-free 44-pin 400 Mil SOJ, 44-pin on I/O to I/O . If Byte High Enable (BHE) is LOW, then data from 1 8 TSOP II, and 48-ball FBGA packages memory appears on I/O to I/O . For more information, see the 9 16 Truth Table on page 10 for a complete description of Read and Write modes. The input and output pins (I/O through I/O ) are placed in a 1 16 high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). Logic Block Diagram DATA IN DRIVERS A 7 A 6 A 5 64K x 16 A 4 I/O I/O 0 7 RAM Array A 3 A I/O I/O 2 8 15 A 1 A 0 COLUMN DECODER BHE WE CE OE BLE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05132 Rev. *O Revised October 10, 2011 + Feedback ROW DECODER A 8 A 9 A 10 A 11 A 12 A 13 A 14 A 15 SENSE AMPSCY7C1021CV33 Contents Selection Guide ................................................................3 Ordering Information ...................................................... 11 Pin Configuration .............................................................3 Ordering Code Definitions ......................................... 11 Pin Definitions ..................................................................4 Package Diagrams .......................................................... 12 Maximum Ratings .............................................................5 Acronyms ........................................................................15 Operating Range ...............................................................5 Document Conventions ................................................. 15 Electrical Characteristics .................................................5 Units of Measure ....................................................... 15 Capacitance ......................................................................6 Document History Page ................................................. 16 Thermal Resistance ..........................................................6 Sales, Solutions, and Legal Information ...................... 17 AC Test Loads and Waveforms .......................................6 Worldwide Sales and Design Support ....................... 17 Switching Characteristics ................................................7 Products ....................................................................17 Switching Waveforms ......................................................8 PSoC Solutions ......................................................... 17 Truth Table ......................................................................10 Document Number: 38-05132 Rev. *O Page 2 of 17 + Feedback