CY7C1021DV33 1-Mbit (64 K x 16) Static RAM 1 Features Functional Description Temperature ranges The CY7C1021DV33 is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has Industrial: 40 C to 85 C an automatic power-down feature that significantly reduces Automotive-A: 40 C to 85 C power consumption when deselected. Pin-and function-compatible with CY7C1021CV33 Writing to the device is accomplished by taking Chip Enable High speed (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O through I/O ), is t = 10 ns 0 7 AA written into the location specified on the address pins (A 0 Low active power through A ). If Byte High Enable (BHE) is LOW, then data 15 I = 60 mA 10 ns from I/O pins (I/O through I/O ) is written into the location CC 8 15 specified on the address pins (A through A ). 0 15 Low CMOS standby power Reading from the device is accomplished by taking Chip I = 3 mA SB2 Enable (CE) and Output Enable (OE) LOW while forcing the 2.0 V data retention Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address Automatic power-down when deselected pins will appear on I/O to I/O . If Byte High Enable (BHE) is 0 7 CMOS for optimum speed/power LOW, then data from memory will appear on I/O to I/O . See 8 15 the truth table at the end of this data sheet for a complete Independent control of upper and lower bits description of Read and Write modes. Available in Pb-free 44-pin 400-Mil wide molded SOJ, The input/output pins (I/O through I/O ) are placed in a 0 15 44-pin TSOP II and 48-ball VFBGA packages high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a Write operation (CE LOW, and WE LOW). The CY7C1021DV33 is available in Pb-free 44-pin 400-Mil wide Molded SOJ, 44-pin TSOP II and 48-ball VFBGA packages. Logic Block Diagram DATA IN DRIVERS A 7 A 6 A 5 64K x 16 A 4 I/O I/O 0 7 RAM Array A 3 A I/O I/O 2 8 15 A 1 A 0 COLUMN DECODER BHE WE CE OE BLE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document : 38-05460 Rev. *G Revised October 25, 2011 ROW DECODER A 8 A 9 A 10 A 11 A 12 A 13 A 14 A 15 SENSE AMPSCY7C1021DV33 Selection Guide 10 (Industrial/Automotive-A) Unit Maximum access time 10 ns Maximum operating current 60 mA Maximum CMOS standby current 3mA 1 Pin Configuration SOJ/TSOP II 48-ball VFBGA Top View Top View A A 1 44 4 5 1 4 2 3 5 6 A A 2 43 3 6 A A 3 42 7 2 A A A BLE OE NC 0 2 A A 1 4 OE 1 41 A 5 40 BHE 0 I/O 6 39 BHE A A CE BLE CE I/O B 8 3 4 0 I/O 7 38 I/O 0 15 I/O 8 37 I/O 1 14 I/O C I/O A A I/O I/O 10 5 6 9 2 1 I/O 9 36 I/O 2 13 I/O 10 I/O 35 3 12 I/O A V I/O NC V 3 CC D V SS 11 7 11 34 V CC SS V 12 SS 33 V CC I/O 13 32 NC 4 I/O V I/O NC I/O V E 11 CC SS 12 4 I/O 14 I/O 5 31 10 I/O I/O 15 30 6 9 I/O F I/O A A I/O I/O 6 14 15 5 I/O 14 13 16 29 I/O 7 8 WE 17 28 NC A 18 27 A A A I/O G 15 I/O NC WE 8 13 7 15 12 A 26 A 14 19 9 A A 13 20 25 10 A A A A NC NC 9 10 11 H A 8 A 12 21 24 11 NC 22 23 NC Notes 1. NC pins are not connected on the die. Document : 38-05460 Rev. *G Page 2 of 13