CY7C1041D 4-Mbit (256 K 16) Static RAM 4-Mbit (256 K 16) Static RAM specified on the address pins (A through A ). If Byte High Features 0 17 Enable (BHE) is LOW, then data from I/O pins (I/O through 8 I/O ) is written into the location specified on the address pins Pin-and function-compatible with CY7C1041B 15 (A through A ). 0 17 High speed Reading from the device is accomplished by taking Chip Enable t = 10 ns AA (CE) and Output Enable (OE) LOW while forcing the Write Low active power Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will I = 90 mA at 10 ns (Industrial) CC appear on I/O to I/O . If Byte High Enable (BHE) is LOW, then 0 7 Low CMOS standby power data from memory will appear on I/O to I/O . See the truth table 8 15 I = 10 mA at the back of this data sheet for a complete description of read SB2 and write modes. 2.0 V data retention The input/output pins (I/O through I/O ) are placed in a 0 15 Automatic power-down when deselected high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are TTL-compatible inputs and outputs disabled (BHE, BLE HIGH), or during a write operation (CE LOW, Easy memory expansion with CE and OE features and WE LOW). Available in Pb-free 44-pin (400-Mil) Molded SOJ and 44-pin The CY7C1041D is available in a standard 44-pin 400-mil-wide TSOP II packages body width SOJ and 44-pin TSOP II package with center power and ground (revolutionary) pinout. Functional Description The CY7C1041D is suitable for interfacing with processors that have TTL I/P levels. It is not suitable for processors that require 1 The CY7C1041D is a high-performance CMOS static RAM CMOS I/P levels. Please see Electrical Characteristics on page organized as 256K words by 16 bits. Writing to the device is 4 for more details and suggested alternatives. accomplished by taking Chip Enable (CE) and Write Enable For a complete list of related documentation, click here. (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O through I/O ), is written into the location 0 7 Logic Block Diagram INPUT BUFFER A 0 A 1 A 2 I/O I/O 0 7 A 3 256K x 16 A 4 A I/O I/O 5 8 15 A 6 A 7 A 8 COLUMN DECODER BHE WE CE OE BLE Note 1. For guidelines on SRAM system design, please refer to the System Design Guidelines Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05472 Rev. *I Revised November 24, 2014 ROW DECODER A 9 A 10 A 11 A12 A 13 A 14 A 15 A 16 A 17 SENSE AMPSCY7C1041D Contents Pin Configuration .............................................................3 Ordering Information ...................................................... 11 Selection Guide ................................................................3 Ordering Code Definitions ......................................... 11 Maximum Ratings .............................................................4 Package Diagrams .......................................................... 12 Operating Range ...............................................................4 Acronyms ........................................................................13 Electrical Characteristics .................................................4 Document Conventions ................................................. 13 Capacitance ......................................................................5 Units of Measure ....................................................... 13 Thermal Resistance ..........................................................5 Document History Page ................................................. 14 AC Test Loads and Waveforms .......................................5 Sales, Solutions, and Legal Information ...................... 16 Data Retention Characteristics .......................................6 Worldwide Sales and Design Support ....................... 16 Data Retention Waveform ................................................6 Products ....................................................................16 Switching Characteristics ................................................7 PSoC Solutions ...................................................... 16 Switching Waveforms ......................................................8 Cypress Developer Community ................................. 16 Truth Table ......................................................................11 Technical Support ..................................................... 16 Document Number: 38-05472 Rev. *I Page 2 of 16