Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY7C1051DV33 8-Mbit (512 K 16) Static RAM 8-Mbit (512K x 16) Static RAM Features Functional Description Temperature ranges The CY7C1051DV33 is a high performance CMOS Static RAM organized as 512 K words by 16-bits. 40 C to 85 C To write to the device, take Chip Enable (CE) and Write Enable High speed (WE) inputs LOW. If Byte LOW Enable (BLE) is LOW, then data t = 10 ns AA from I/O pins (I/O I/O ), is written into the location specified on 0 7 Low active power the address pins (A A ). If Byte HIGH Enable (BHE) is LOW, 0 18 then data from I/O pins (I/O I/O ) is written into the location I = 110 mA at f = 100 MHz 8 15 CC specified on the address pins (A A ). 0 18 Low CMOS standby power To read from the device, take Chip Enable (CE) and Output I = 20 mA SB2 Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If 2.0-V data retention Byte LOW Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O I/O . If 0 7 Automatic power-down when deselected Byte HIGH Enable (BHE) is LOW, then data from memory appears on I/O to I/O . See the Truth Table on page 10 for a Transistor-transistor logic (TTL)-compatible inputs and outputs 8 15 complete description of read and write modes. Easy memory expansion with CE and OE features The input/output pins (I/O I/O ) are placed in a 0 15 Available in Pb-free 48-ball fine ball grid array (FBGA) and high-impedance state when the device is deselected (CE HIGH), 44-pin thin small outline package (TSOP) II packages the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or a write operation (CE LOW, and WE LOW) is in progress. The CY7C1051DV33 is available in a 44-pin TSOP II package with center power and ground (revolutionary) pinout and a 48-ball FBGA package. For a complete list of related documentation,click here. Logic Block Diagram INPUT BUFFER A 0 A 1 A 2 I/O I/O A 0 7 3 512 K 16 A 4 ARRAY I/O I/O A 5 8 15 A 6 A 7 A 8 COLUMN DECODER BHE WE CE OE BLE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-00063 Rev. *J Revised January 16, 2015 ROW DECODER A 9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 A 17 A 18 SENSE AMPS