CY7C1051DV33 8-Mbit (512 K 16) Static RAM 8-Mbit (512K x 16) Static RAM Features Functional Description Temperature ranges The CY7C1051DV33 is a high performance CMOS Static RAM organized as 512 K words by 16-bits. 40 C to 85 C To write to the device, take Chip Enable (CE) and Write Enable High speed (WE) inputs LOW. If Byte LOW Enable (BLE) is LOW, then t = 10 ns AA data from I/O pins (I/O I/O ), is written into the location 0 7 Low active power specified on the address pins (A A ). If Byte HIGH Enable 0 18 (BHE) is LOW, then data from I/O pins (I/O I/O ) is written I = 110 mA at f = 100 MHz 8 15 CC into the location specified on the address pins (A A ). 0 18 Low CMOS standby power To read from the device, take Chip Enable (CE) and Output I = 20 mA SB2 Enable (OE) LOW while forcing the Write Enable (WE) HIGH. 2.0-V data retention If Byte LOW Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O I/O . If 0 7 Automatic power-down when deselected Byte HIGH Enable (BHE) is LOW, then data from memory appears on I/O to I/O . See the Truth Table on page 9 for Transistor-transistor logic (TTL)-compatible inputs and 8 15 a complete description of read and write modes. outputs The input/output pins (I/O I/O ) are placed in a 0 15 Easy memory expansion with CE and OE features high-impedance state when the device is deselected (CE Available in Pb-free 48-ball fine ball grid array (FBGA) and HIGH), the outputs are disabled (OE HIGH), the BHE and BLE 44-pin thin small outline package (TSOP) II packages are disabled (BHE, BLE HIGH), or a write operation (CE LOW, and WE LOW) is in progress. The CY7C1051DV33 is available in a 44-pin TSOP II package with center power and ground (revolutionary) pinout and a 48-ball FBGA package. Logic Block Diagram INPUT BUFFER A 0 A 1 A 2 I/O I/O A 0 7 3 512 K 16 A 4 ARRAY I/O I/O A 5 8 15 A 6 A 7 A 8 COLUMN DECODER BHE WE CE OE BLE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document : 001-00063 Rev. *H Revised September 22, 2011 ROW DECODER A 9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 A 17 A 18 SENSE AMPSCY7C1051DV33 Contents Pin Configurations ...........................................................3 Write Cycle No. 1 (CE Controlled) ............................... 8 Selection Guide ................................................................3 Write Cycle No. 2 (BLE or BHE Controlled) ................ 8 Maximum Ratings .............................................................4 Write Cycle No. 3 (WE Controlled, OE LOW) ............. 9 Operating Range ...............................................................4 Truth Table ........................................................................ 9 DC Electrical Characteristics Ordering Information ...................................................... 10 Over the Operating Range ...............................................4 Ordering Code Definitions ......................................... 10 Capacitance ......................................................................4 Package Diagrams .......................................................... 11 Thermal Resistance ..........................................................4 Acronyms ........................................................................13 AC Test Loads and Waveforms .......................................5 Document Conventions ................................................. 13 Data Retention Characteristics .......................................5 Units of Measure ....................................................... 13 Over the Operating Range ...............................................5 Document History Page ................................................. 14 Data Retention Waveform ................................................5 Sales, Solutions, and Legal Information ...................... 15 AC Switching Characteristics .........................................6 Worldwide Sales and Design Support ....................... 15 Switching Waveforms ......................................................7 Products ....................................................................15 Read Cycle No. 1 ........................................................7 PSoC Solutions ......................................................... 15 Read Cycle No. 2 (OE Controlled) ..............................7 Document : 001-00063 Rev. *H Page 2 of 15