Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY7C1059DV33 8-Mbit (1M 8) Static RAM Features Functional Description High speed The CY7C1059DV33 is a high performance CMOS Static RAM organized as 1M words by 8 bits. Easy memory expansion is t = 10 ns AA provided by an active LOW Chip Enable (CE), an active LOW Low active power Output Enable (OE), and tri-state drivers. To write to the device, I = 110 mA at f = 100 MHz take Chip Enable (CE) and Write Enable (WE) inputs LOW. Data CC on the eight I/O pins (I/O through I/O ) is then written into the 0 7 Low CMOS standby power location specified on the address pins (A through A ). 0 19 I = 20 mA SB2 To read from the device, take Chip Enable (CE) and Output 2.0 V data retention Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified Automatic power down when deselected by the address pins appear on the I/O pins. TTL-compatible inputs and outputs The eight input or output pins (I/O through I/O ) are placed in a 0 7 high impedance state when the device is deselected (CE HIGH), Easy memory expansion with CE and OE features the outputs are disabled (OE HIGH), or a write operation is in Available in Pb-free 44-pin TSOP-II package progress (CE LOW and WE LOW). Offered in standard and high reliability (Q) grades The CY7C1059DV33 is available in 44-pin TSOP-II package with center power and ground (revolutionary) pinout. For a complete list of related documentation, click here. Logic Block Diagram IO INPUT BUFFER 0 A 0 A 1 IO A 1 2 A 3 IO 2 A 4 A 5 1M x 8 IO 3 A 6 A 7 IO ARRAY 4 A 8 A 9 IO 5 A 10 IO 6 CE IO POWER 7 COLUMN DECODER WE DOWN OE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-00061 Rev. *J Revised January 16, 2015 ROW DECODER A 11 A 12 A 13 A 14 A 15 A 16 A 17 A 18 A 19 SENSE AMPS