CY7C1061AV33 16-Mbit (1 M 16) Static RAM 16-Mbit (1 M 16) Static RAM Features Functional Description High speed The CY7C1061AV33 is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits. t = 10 ns AA To write to the device, enable the chip (CE LOW and CE HIGH) 1 2 Low active power while forcing the Write Enable (WE) input LOW. If Byte Low 990 mW (max) Enable (BLE) is LOW, then data from I/O pins (I/O through I/O ), 0 7 Operating voltages of 3.3 0.3 V is written into the location specified on the address pins (A 0 through A ). If Byte High Enable (BHE) is LOW, then data from 19 2.0 V data retention I/O pins (I/O through I/O ) is written into the location specified 8 15 on the address pins (A through A ). Automatic power down when deselected 0 19 To read from the device, enable the chip by taking CE LOW and 1 TTL compatible inputs and outputs CE HIGH while forcing the Output Enable (OE) LOW and the 2 Easy memory expansion with CE and CE features Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then 1 2 data from the memory location specified by the address pins will Available in Pb-free and non Pb-free 54-pin TSOP II package appear on I/O to I/O . If Byte High Enable (BHE) is LOW, then 0 7 and non Pb-free 60-ball fine-pitch ball grid array (FBGA) data from memory will appear on I/O to I/O . See Truth Table 8 15 package on page 11 for a complete description of Read and Write modes. The input/output pins (I/O through I/O ) are placed in a 0 15 high-impedance state when the device is deselected (CE 1 HIGH/CE LOW), the outputs are disabled (OE HIGH), the BHE 2 and BLE are disabled (BHE, BLE HIGH), or a Write operation is in progress (CE LOW, CE HIGH, and WE LOW). 1 2 For a complete list of related documentation, click here. Logic Block Diagram INPUT BUFFER A 0 A 1 A 2 A 3 I/O I/O 1M x 16 0 7 A 4 ARRAY A 5 I/O I/O 8 15 A 6 A 7 A 8 A 9 COLUMN DECODER BHE WE CE 2 CE 1 OE BLE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05256 Rev. *M Revised January 16, 2015 ROW DECODER A 10 A 11 A 12 A 13 A 14 A 15 A 16 A 17 A 18 A 19 SENSE AMPSCY7C1061AV33 Contents Selection Guide ................................................................3 Package Diagrams .......................................................... 13 Pin Configurations ...........................................................3 Acronyms ........................................................................15 Maximum Ratings .............................................................5 Document Conventions ................................................. 15 Operating Range ...............................................................5 Units of Measure ....................................................... 15 DC Electrical Characteristics ..........................................5 Document History Page ................................................. 16 Capacitance ......................................................................6 Sales, Solutions, and Legal Information ...................... 17 AC Test Loads and Waveforms .......................................6 Worldwide Sales and Design Support ....................... 17 Data Retention Waveform ................................................6 Products ....................................................................17 AC Switching Characteristics .........................................7 PSoC Solutions ...................................................... 17 Switching Waveforms ......................................................8 Cypress Developer Community ................................. 17 Truth Table ......................................................................11 Technical Support ..................................................... 17 Ordering Information ......................................................12 Ordering Code Definitions .........................................12 Document Number: 38-05256 Rev. *M Page 2 of 17