CY7C1061G/CY7C1061GE
16-Mbit (1 M words 16 bit) Static RAM
with Error-Correcting Code (ECC)
16-Mbit (1 M words 16 bit) Static RAM with Error-Correcting Code (ECC)
To access devices with a single chip enable input, assert the chip
Features
enable (CE) input LOW. To access dual chip enable devices,
High speed
assert both chip enable inputs CE as LOW and CE as HIGH.
1 2
t = 10 ns/15 ns
AA
To perform data writes, assert the Write Enable (WE) input LOW,
and provide the data and address on the device data pins (I/O
Embedded error-correcting code (ECC) for single-bit error
0
through I/O ) and address pins (A through A ) respectively.
correction
15 0 19
The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs
Low active and standby currents
control byte writes, and write data on the corresponding I/O lines
I = 90-mA typical at 100 MHz
CC
to the memory location specified. BHE controls I/O through
8
I = 20-mA typical
SB2 I/O and BLE controls I/O through I/O .
15 0 7
Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and
To perform data reads, assert the Output Enable (OE) input and
4.5 V to 5.5 V
provide the required address on the address lines. Read data is
accessible on I/O lines (I/O through I/O ). You can perform
0 15
1.0-V data retention
byte accesses by asserting the required byte enable signal (BHE
Transistor-transistor logic (TTL) compatible inputs and outputs
or BLE) to read either the upper byte or the lower byte of data
from the specified address location.
Error indication (ERR) pin to indicate 1-bit error detection and
correction through I/O ) are placed in a high-impedance state
All I/Os (I/O
0 15
when the device is deselected (CE HIGH for a single chip enable
Available in Pb-free 48-pin TSOP I, 54-pin TSOP II, and 48-ball
HIGH / CE LOW for a dual chip enable device),
device and CE
1 2
VFBGA packages
or control signals are de-asserted (OE, BLE, BHE).
Functional Description
On the CY7C1061GE devices, the detection and correction of a
single-bit error in the accessed location is indicated by the
CY7C1061G and CY7C1061GE are high-performance CMOS
assertion of the ERR output (ERR = High). See the Truth Table
[1]
fast static RAM devices with embedded ECC . Both devices are
on page 16 for a complete description of read and write modes.
offered in single and dual chip enable options and in multiple pin
The logic block diagrams are on page 2.
configurations. The CY7C1061GE device includes an ERR pin
that signals a single-bit error-detection and correction event
The CY7C1061G and CY7C1061GE devices are available in
during a read cycle.
48-pin TSOP I, 54-pin TSOP II, and 48-ball VFBGA packages.
For a complete list of related documentation, click here.
Product Portfolio
Current Consumption
Features and Options Speed
Operating I , (mA)
V Range CC
CC
Product (see Pin Configurations Range (ns) Standby, I (mA)
SB2
(V)
f = f
on page 4) 10/15
max
[2] [2]
Typ Max Typ Max
Industrial 1.65 V2.2 V 15 70 80 20 30
CY7C1061G18 Single or dual chip
enables
CY7C1061G(E)30 2.2 V3.6 V 10 90 110
CY7C1061G Optional ERR pins 4.5 V5.5 V 10 90 110
Address MSB A pin
19
placement options
compatible with Cypress
and other vendors
Notes
1. This device does not support automatic write-back on error detection.
2. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for a V range of 1.65 V2.2 V),
CC CC
V = 3 V (for a V range of 2.2 V3.6 V), and V = 5 V (for a V range of 4.5 V5.5 V), T = 25 C.
CC CC CC CC A
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 001-81540 Rev. *P Revised June 9, 2015CY7C1061G/CY7C1061GE
Logic Block Diagram CY7C1061G
Logic Block Diagram CY7C1061GE
Document Number: 001-81540 Rev. *P Page 2 of 24