CY7C1062DV33 16-Mbit (512 K 32) Static RAM 16-Mbit (512 K 32) Static RAM Features Functional Description High speed The CY7C1062DV33 is a high performance CMOS Static RAM organized as 524,288 words by 32 bits. t = 10 ns AA To write to the device, take Chip Enables (CE CE and CE 1, 2, 3 Low active power LOW) and Write Enable (WE) input LOW. If Byte Enable A (B ) A I = 175 mA at 100 MHz CC is LOW, then data from I/O pins (I/O through I/O ) is written into 0 7 Low complementary metal oxide semiconductor (CMOS) the location specified on the address pins (A through A ). If 0 18 standby power Byte Enable B (B ) is LOW, then data from I/O pins (I/O through B 8 I/O ) is written into the location specified on the address pins I = 25 mA 15 SB2 (A through A ). Likewise, B and B correspond with the I/O 0 18 C D Operating voltages of 3.3 0.3 V pins I/O to I/O and I/O to I/O , respectively. 16 23 24 31 2.0 V data retention To read from the device, take Chip Enables (CE CE , and CE 1, 2 3 LOW) and Output Enable (OE) LOW while forcing the Write Automatic power down when deselected Enable (WE) HIGH. If the first B is LOW, then data from the A memory location specified by the address pins appear on I/O to Transistor-transistor logic (TTL) compatible inputs and outputs 0 I/O . If B is LOW, then data from memory appears on I/O to 7 B 8 Easy memory expansion with CE , CE , and CE features 1 2 3 I/O . Likewise, B and B correspond to the third and fourth 15 c D bytes. See Truth Table on page 10 for a complete description of Available in Pb-free 119-ball plastic ball grid array (PBGA) read and write modes. package The input and output pins (I/O through I/O ) are placed in a 0 31 high impedance state when the device is deselected (CE CE 1, 2, or CE HIGH), the outputs are disabled (OE HIGH), the byte 3 selects are disabled (B HIGH), or during a write operation A-D (CE CE and CE LOW and WE LOW). 1, 2 3 For a complete list of related documentation, click here. Logic Block Diagram WE CE 1 CE 2 INPUT BUFFERS CE 3 OE B A B B B C B D 512 K x 32 I/O I/O A 0 31 (9:0) ARRAY COLUMN DECODER A (18:10) Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05477 Rev. *I Revised November 19, 2014 ROW DECODER SENSE AMPS OUTPUT BUFFERS CONTROL LOGICCY7C1062DV33 Contents Selection Guide ................................................................3 Ordering Information ...................................................... 11 Pin Configuration .............................................................3 Ordering Code Definitions ......................................... 11 Maximum Ratings .............................................................4 Package Diagram ............................................................ 12 Operating Range ...............................................................4 Acronyms ........................................................................13 DC Electrical Characteristics ..........................................4 Document Conventions ................................................. 13 Capacitance ......................................................................5 Units of Measure ....................................................... 13 Thermal Resistance ..........................................................5 Document History ........................................................... 14 AC Test Loads and Waveforms .......................................5 Sales, Solutions, and Legal Information ...................... 15 AC Switching Characteristics .........................................6 Worldwide Sales and Design Support ....................... 15 Data Retention Characteristics .......................................7 Products ....................................................................15 Over the Operating Range ...............................................7 PSoC Solutions ......................................................... 15 Data Retention Waveform ................................................7 Switching Waveforms ......................................................7 Truth Table ......................................................................10 Document Number: 38-05477 Rev. *I Page 2 of 15