CY7C1069G CY7C1069GE 16-Mbit (2M words 8 bit) Static RAM with Error-Correcting Code (ECC) 16-Mbit (2M words 8 bit) Static RAM with Error-Correcting Code (ECC) processor in the case of an ECC error-detection and correction Features event. High speed To write to the device, take Chip Enables (CE LOW and CE 1 2 t = 10 ns AA HIGH) and Write Enable (WE) input LOW. Data on the eight I/O pins (I/O through I/O ) is then written into the location specified Embedded error-correcting code (ECC) for single-bit error 0 7 on the address pins (A through A ). correction 0 20 To read from the device, take Chip Enables (CE LOW and CE 1 2 Low active and standby currents HIGH) and Output Enable (OE) LOW while forcing the Write I = 90 mA typical at 100 MHz CC Enable (WE) HIGH. Under these conditions, the contents of the I = 20 mA typical SB2 memory location specified by the address pins will appear on the I/O pins. See Truth Table CY7C1069G/CY7C1069GE on page Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, 4.5 V 14 for a complete description of Read and Write modes. The to 5.5 V input and output pins (I/O through I/O ) are placed in a high 0 7 1.0-V data retention impedance state when the device is deselected (CE HIGH or 1 CE LOW), the outputs are disabled (OE HIGH), or during a write 2 Transistor-transistor logic (TTL) compatible inputs and outputs operation (CE LOW, CE HIGH, and WE LOW). 1 2 ERR pin to indicate 1-bit error detection and correction On CY7C1069GE devices, the detection and correction of a single-bit error in the accessed location is indicated by the Available in Pb-free 54-pin TSOP II, and 48-ball VFBGA 1 assertion of the ERR output (ERR = High) . packages All I/Os (I/O through I/O ) are placed in a high impedance state 0 7 Functional Description when the device is deselected (CE HIGH or CE LOW), and 1 2 control signals are de-asserted (CE / CE , OE, WE). 1 2 The CY7C1069G and CY7C1069GE are dual chip enable CY7C1069G and CY7C1069GE devices are available in a high-performance CMOS fast static RAM devices with 54-pin TSOP II package with center power and ground embedded ECC. The CY7C1069G device is available in (revolutionary) pinout, and in a 48-ball VFBGA package. standard pin configurations. The CY7C1069GE device includes For a complete list of related documentation, here. a single bit error indication pin (ERR) that signals the host Note 1. Automatic write back on error detection feature is not supported in this device. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-81539 Rev. *J Revised December 5, 2017CY7C1069G CY7C1069GE Logic Block Diagram CY7C1069G DATA IN ECCENCODER DRIVERS A0 A1 A2 A3 I/O I/O 2Mx8 0 7 A4 RAMARRAY A5 A6 A7 A8 A9 COLUMN DECODER WE CE 2 CE OE 1 Logic Block Diagram CY7C1069GE DATA IN ECCENCODER DRIVERS A0 A1 A2 A3 2Mx8 I/O I/O 0 7 A4 RAMARRAY A5 ERR A6 A7 A8 A9 COLUMN WE CE 2 DECODER CE 1 OE Document Number: 001-81539 Rev. *J Page 2 of 20 ROWDECODER ROWDECODER A10 A10 A11 A11 A12 A12 A13 A13 A14 A14 A15 A15 A16 A16 A17 A17 A18 A18 A19 A19 A20 SENSE A20 SENSE AMPLIFIERS AMPLIFIERS ECCDECODER ECCDECODER