Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY7C1079DV33 32-Mbit (4 M 8) Static RAM 32-Mbit (4 M 8) Static RAM Features Functional Description High Speed The CY7C1079DV33 is a high performance CMOS Static RAM organized as 4,194,304 words by 8 bits. t = 12 ns AA 1 To write to the device, take Chip Enable (CE ) and Write Enable Low Active Power (WE) input LOW. Data on the eight I/O pins (I/O through I/O ) 0 7 I = 250 mA at 12 ns CC is then written into the location specified on the address pins (A 0 Low CMOS Standby Power through A ). 21 1 I = 50 mA SB2 To read from the device, take Chip Enable (CE ) LOW and Output Enable (OE) LOW while forcing the Write Enable (WE) Operating Voltages of 3.3 0.3 V HIGH. Under these conditions, the contents of the memory 2.0 V Data Retention location specified by the address pins appear on the I/O pins. See Truth Table (Single Chip Enable) on page 10 for a complete Automatic Power Down when Deselected description of Read and Write modes. TTL Compatible Inputs and Outputs The input and output pins (I/O through I/O ) are placed in a high 0 7 1 impedance state when the device is deselected (CE HIGH), Available in Pb-free 48-ball FBGA Package the outputs are disabled (OE HIGH), or during a write operation 1 (CE LOW and WE LOW). The CY7C1079DV33 is available in a 48-ball FBGA package. For a complete list of related documentation, click here. Logic Block Diagram INPUT BUFFER A 0 A 1 A 2 A 3 IO IO 4M x 8 0 7 A 4 ARRAY A 5 A 6 A 7 A 8 A 9 WE COLUMN DECODER OE 1 CE Note 1. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE and 1 CE such that when CE is LOW and CE is HIGH, CE is LOW. For all other cases CE is HIGH. 2 1 2 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-50282 Rev. *F Revised November 28, 2014 ROW DECODER A 10 A 11 A 12 A 13 A 14 A 15 A 16 A 17 A 18 A 19 A 20 A 21 SENSE AMPS