CY7C1243KV18/CY7C1245KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) 36-Mbit QDR II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations Separate independent read and write data ports With Read Cycle Latency of 2.0 cycles: Supports concurrent transactions CY7C1243KV18 2M 18 450 MHz clock for high bandwidth CY7C1245KV18 1M 36 Four-word burst for reducing address bus frequency Functional Description Double data rate (DDR) interfaces on both read and write ports The CY7C1243KV18, and CY7C1245KV18 are 1.8 V (data transferred at 900 MHz) at 450 MHz synchronous pipelined SRAMs, equipped with QDR II+ Available in 2.0 clock cycle latency architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to Two input clocks (K and K) for precise DDR timing access the memory array. The read port has dedicated data SRAM uses rising edges only outputs to support read operations and the write port has Echo clocks (CQ and CQ) simplify data capture in high speed dedicated data inputs to support write operations. QDR II+ systems architecture has separate data inputs and data outputs to Data valid pin (QVLD) to indicate valid data on the output completely eliminate the need to turnaround the data bus that exists with common I/O devices. Each port is accessed through Single multiplexed address input bus latches address inputs a common address bus. Addresses for read and write addresses for read and write ports are latched on alternate rising edges of the input (K) clock. Separate port selects for depth expansion Accesses to the QDR II+ read and write ports are completely independent of one another. To maximize data throughput, both Synchronous internally self-timed writes read and write ports are equipped with DDR interfaces. Each QDR II+ operates with 2.0 cycle read latency when DOFF is address location is associated with four 18-bit words asserted HIGH (CY7C1243KV18), or 36-bit words (CY7C1245KV18) that burst Operates similar to QDR I device with 1 cycle read latency when sequentially into or out of the device. Because data is transferred DOFF is asserted LOW into and out of the device on every rising edge of both input clocks (K and K), memory bandwidth is maximized while Available in 18, and 36 configurations simplifying system design by eliminating bus turnarounds. Full data coherency, providing most current data Depth expansion is accomplished with port selects, which 1 Core V = 1.8 V 0.1 V I/O V = 1.4 V to V enables each port to operate independently. DD DDQ DD Supports both 1.5 V and 1.8 V I/O supply All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output HSTL inputs and variable drive HSTL output buffers registers controlled by the K or K input clocks. Writes are Available in 165-ball FBGA package (13 15 1.4 mm) conducted with on-chip synchronous self-timed write circuitry. Offered in both Pb-free and non Pb-free packages For a complete list of related documentation, click here. JTAG 1149.1 compatible test access port Phase-locked loop (PLL) for accurate data placement Selection Guide Description 450 MHz 400 MHz Unit Maximum operating frequency 450 400 MHz Maximum operating current 18 720 660 mA 36 1020 920 Note 1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V = 1.4 V to V . DDQ DD Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-57832 Rev. *J Revised November 29, 2017512K x 18 Array 256K x 36 Array 512K x 18 Array 256K x 36 Array 512K x 18 Array 256K x 36 Array 512K x 18 Array 256K x 36 Array CY7C1243KV18/CY7C1245KV18 Logic Block Diagram CY7C1243KV18 18 D 17:0 Write Write Write Write 19 Address A Reg Reg Reg Reg (18:0) Register 19 Address A (18:0) Register RPS K Control CLK K Logic Gen. DOFF Read Data Reg. CQ 72 V 36 REF 18 CQ Reg. Reg. Control WPS 18 Logic 18 18 36 BWS Q Reg. 1:0 17:0 18 QVLD Logic Block Diagram CY7C1245KV18 36 D 35:0 Write Write Write Write 18 Address A Reg Reg Reg Reg (17:0) Register 18 Address A (17:0) Register K RPS Control CLK K Logic Gen. DOFF Read Data Reg. CQ 144 V 72 REF CQ 36 Reg. Reg. Control WPS 36 Logic 36 72 36 BWS Q Reg. 3:0 35:0 36 QVLD Document Number: 001-57832 Rev. *J Page 2 of 31 Write Add. Decode Write Add. Decode Read Add. Decode Read Add. Decode