CY7C1262XV18-366BZXC Infineon

CY7C1262XV18 CY7C1264XV18 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate independent read and write data ports With Read Cycle Latency of 2.5 cycles: Supports concurrent transactions CY7C1262XV18 2 M 18 450 MHz clock for high bandwidth CY7C1264XV18 1 M 36 Two-word burst for reducing address bus frequency Functional Description Double Data Rate (DDR) interfaces on both read and write ports The CY7C1262XV18, and CY7C1264XV18 are 1.8V (data transferred at 900 MHz) at 450 MHz Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture Available in 2.5 clock cycle latency consists of two separate ports: the read port and the write port to Two input clocks (K and K) for precise DDR timing access the memory array. The read port has dedicated data SRAM uses rising edges only outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ Echo clocks (CQ and CQ) simplify data capture in high speed architecture has separate data inputs and data outputs to systems completely eliminate the need to turnaround the data bus that exists with common I/O devices. Access to each port is through Data valid pin (QVLD) to indicate valid data on the output a common address bus. Addresses for read and write addresses Single multiplexed address input bus latches address inputs are latched on alternate rising edges of the input (K) clock. for both read and write ports Accesses to the QDR II+ Xtreme read and write ports are completely independent of one another. To maximize data Separate port selects for depth expansion throughput, both read and write ports are equipped with DDR Synchronous internally self-timed writes interfaces. Each address location is associated with two 18-bit words (CY7C1262XV18), or 36-bit words (CY7C1264XV18) that QDR-II+ Xtreme operates with 2.5 cycle read latency when burst sequentially into or out of the device. Because data can be DOFF is asserted HIGH transferred into and out of the device on every rising edge of both input clocks (K and K), memory bandwidth is maximized while Operates similar to QDR-I device with 1 cycle read latency simplifying system design by eliminating bus turnarounds. when DOFF is asserted LOW Depth expansion is accomplished with port selects, which Available in x18, and x36 configurations enables each port to operate independently. Full data coherency, providing most current data All synchronous inputs pass through input registers controlled by Core V = 1.8 V 0.1 V I/Os V = 1.4 V to 1.6 V the K or K input clocks. All data outputs pass through output DD DDQ registers controlled by the K or K input clocks. Writes are Supports 1.5 V I/O supply conducted with on-chip synchronous self-timed write circuitry. HSTL inputs and variable drive HSTL output buffers For a complete list of related documentation, click here. Available in 165-ball FBGA package (13 15 1.4 mm) Offered in Pb-free packages JTAG 1149.1 compatible test access port Phase-Locked Loop (PLL) for accurate data placement Selection Guide Description 450 MHz 366 MHz Unit Maximum Operating Frequency 450 366 MHz Maximum Operating Current 18 1205 970 mA 36 1445 1165 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-70327 Rev. *G Revised December 22, 20171M x 18 Array 512K x 36 Array 1M x 18 Array 512K x 36 Array CY7C1262XV18 CY7C1264XV18 Logic Block Diagram CY7C1262XV18 18 D 17:0 Write Write 20 Address A Reg Reg (19:0) Register 20 Address A (19:0) Register RPS K Control CLK K Logic Gen. DOFF Read Data Reg. CQ 36 V 18 REF 18 CQ Reg. Reg. Control WPS Logic 18 18 Q BWS Reg. 17:0 1:0 18 QVLD Logic Block Diagram CY7C1264XV18 36 D 35:0 Write Write 19 Address A Reg Reg (18:0) Register 19 Address A (18:0) Register RPS K Control CLK K Logic Gen. DOFF Read Data Reg. CQ 72 V 36 REF 36 CQ Reg. Reg. Control WPS Logic 36 36 Q BWS Reg. 35:0 3:0 36 QVLD Document Number: 001-70327 Rev. *G Page 2 of 29 Write Add. Decode Write Add. Decode Read Add. Decode Read Add. Decode