CY7C1261V18, CY7C1276V18
CY7C1263V18, CY7C1265V18
36-Mbit QDR-II+ SRAM 4-Word Burst
Architecture (2.5 Cycle Read Latency)
Features Configurations
With Read Cycle Latency of 2.5 cycles:
Separate independent read and write data ports
CY7C1261V18 4M x 8
Supports concurrent transactions
CY7C1276V18 4M x 9
300 MHz to 400 MHz clock for high bandwidth
CY7C1263V18 2M x 18
4-Word Burst for reducing address bus frequency
CY7C1265V18 1M x 36
Double Data Rate (DDR) interfaces on both read and write ports
Functional Description
(data transferred at 800 MHz) at 400 MHz
The CY7C1261V18, CY7C1276V18, CY7C1263V18, and
Read latency of 2.5 clock cycles
CY7C1265V18 are 1.8V Synchronous Pipelined SRAMs,
Two input clocks (K and K) for precise DDR timing
equipped with Quad Data Rate-II+ (QDR-II+) architecture.
SRAM uses rising edges only QDR-II+ architecture consists of two separate ports to access
the memory array. The read port has dedicated data outputs to
Echo clocks (CQ and CQ) simplify data capture in high speed
support read operations and the write port has dedicated data
systems
inputs to support write operations. QDR-II+ architecture has
separate data inputs and data outputs to completely eliminate
Single multiplexed address input bus latches address inputs
the need to turn around the data bus required with common IO
for both read and write ports
devices. Each port is accessed through a common address bus.
Separate Port Selects for depth expansion
Addresses for read and write addresses are latched on alternate
rising edges of the input (K) clock. Accesses to the QDR-II+ read
Data valid pin (QVLD) to indicate valid data on the output
and write ports are completely independent of one another. To
Synchronous internally self-timed writes
maximize data throughput, both read and write ports are
equipped with Double Data Rate (DDR) interfaces. Each
Available in x8, x9, x18, and x36 configurations
address location is associated with four 8-bit words
(CY7C1261V18), 9-bit words (CY7C1276V18), 18-bit words
Full data coherency providing most current data
(CY7C1263V18), or 36-bit words (CY7C1265V18) that burst
[1]
Core V = 1.8V 0.1V; IO V = 1.4V to V
DD DDQ DD
sequentially into or out of the device. Because data can be trans-
ferred into and out of the device on every rising edge of both input
HSTL inputs and variable drive HSTL output buffers
clocks (K and K), memory bandwidth is maximized while simpli-
Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
fying system design by eliminating bus turn-arounds.
Depth expansion is accomplished with Port Selects for each port.
Offered in both Pb-free and non Pb-free packages
Port selects enable each port to operate independently.
JTAG 1149.1 compatible test access port
All synchronous inputs pass through input registers controlled by
Delay Lock Loop (DLL) for accurate data placement
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Selection Guide
Description 400 MHz 375 MHz 333 MHz 300 MHz Unit
Maximum Operating Frequency 400 375 333 300 MHz
Maximum Operating Current 1330 1240 1120 1040 mA
Note
1. The QDR consortium specification for V is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting
DDQ
V = 1.4V to V .
DDQ DD
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 001-06366 Rev. *E Revised September 01, 2008
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1M x 8 Array 1M x 9 Array
1M x 8 Array 1M x 9 Array
1M x 8 Array 1M x 9 Array
1M x 8 Array 1M x 9 Array
CY7C1261V18, CY7C1276V18
CY7C1263V18, CY7C1265V18
Logic Block Diagram (CY7C1261V18)
D
[7:0]
8
Write Write Write Write
Address
A
Reg Reg Reg Reg (19:0)
Address Register 20
Register
A
(19:0)
20
K RPS
Control
CLK
K
Logic
Gen.
DOFF
Read Data Reg.
CQ
CQ
32
16
V
REF
Reg.
Reg.
WPS
Control
Q
[7:0]
Logic 16
NWS
[1:0] Reg. 8
8
QVLD
Logic Block Diagram (CY7C1276V18)
D
[8:0]
9
Write Write Write Write
Address
A
Reg Reg Reg Reg (19:0)
20
Address Register
Register
A
(19:0)
20
RPS
K
Control
CLK
K
Logic
Gen.
DOFF
Read Data Reg.
CQ
CQ
36
18
V
REF
Reg. Reg.
WPS
Control
Q
[8:0]
18
BWS Logic
[0]
Reg. 9
9
QVLD
Document Number: 001-06366 Rev. *E Page 2 of 29
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Write Add. Decode Write Add. Decode
Read Add. Decode Read Add. Decode