CY7C1303BV25-167BZC Infineon

CY7C1303BV25 18-Mbit Burst of Two-Pipelined SRAM with QDR Architecture 18-Mbit Burst of Two-Pipelined SRAM with QDR Architecture Features Functional Description Separate independent read and write data ports The CY7C1303BV25 is 2.5V synchronous pipelined SRAM equipped with QDR architecture. QDR architecture consists of Supports concurrent transactions two separate ports to access the memory array. The read port 167 MHz clock for high bandwidth has dedicated data outputs to support read operations and the 2.5 ns clock-to-valid access time write port has dedicated data inputs to support write operations. Access to each port is accomplished through a common address Two word burst on all accesses bus. The Read address is latched on the rising edge of the K Double data rate (DDR) interfaces on both read and write ports clock and the Write address is latched on the rising edge of K (data transferred at 333 MHz) at 167 MHz clock. QDR has separate data inputs and data outputs to completely eliminate the need to turn around the data bus Two input clocks (K and K) for precise DDR timing required with common I/O devices. Accesses to the SRAM uses rising edges only CY7C1303BV25 Read and Write ports are completely independent of one another. All accesses are initiated Two input clocks for output data (C and C) to minimize clock synchronously on the rising edge of the positive input clock (K). skew and flight time mismatches. In order to maximize data throughput, both Read and Write ports Single multiplexed address input bus latches address inputs are equipped with Double Data Rate (DDR) interfaces. for both read and write ports Therefore, data can be transferred into the device on every rising edge of both input clocks (K and K) and out of the device on every Separate port selects for depth expansion rising edge of the output clock (C and C, or K and K when in single clock mode) thereby maximizing performance while Synchronous internally self-timed writes simplifying system design. Each address location is associated 2.5 V core power supply with HSTL inputs and outputs with two 18-bit words (CY7C1303BV25) that burst sequentially into or out of the device. Available in 165-ball FBGA package (13 15 1.4 mm) Depth expansion is accomplished with a port select input for Variable drive HSTL output buffers each port. Each Port Selects allow each port to operate independently. Expanded HSTL output voltage (1.4 V to 1.9 V) All synchronous inputs pass through input registers controlled by JTAG Interface the K or K input clocks. All data outputs pass through output Variable Impedance HSTL registers controlled by the C or C input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Configurations For a complete list of related documentation, click here. CY7C1303BV25 1 M 18 Selection Guide Description CY7C1303BV25-167 Unit Maximum operating frequency 167 MHz Maximum operating current 500 mA Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05627 Rev. *H Revised November 11, 2014CY7C1303BV25 Logic Block Diagram CY7C1303BV25 D 17:0 18 Write Write Data Reg Data Reg Address A Register (18:0) Address A (18:0) 19 Register 19 512 K 18 512 K 18 Memory Memory Array Array K CLK RPS Control K Gen. Logic C Read Data Reg. C 36 18 V 18 REF Reg. Reg. 18 Control WPS 18 Logic BWS 0 Reg. Q BWS 17:0 1 18 Document Number: 38-05627 Rev. *H Page 2 of 26 Write Add. Decode Read Add. Decode