CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 1K x 8 Dual-Port Static RAM Features Functional Description 1 True dual-ported memory cells, which allow simultaneous The CY7C130/130A/CY7C131/131A/CY7C140 and CY7C141 reads of the same memory location are high speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in 1K x 8 organization memory. The CY7C130/130A/ CY7C131/131A can be used as either a standalone 8-bit dual-port static RAM or as a master 0.65 micron CMOS for optimum speed and power dual-port RAM in conjunction with the CY7C140/CY7C141 slave High speed access: 15 ns dual-port device in systems requiring 16-bit or greater word widths. It is the solution to applications requiring shared or Low operating power: I = 110 mA (maximum) CC buffered data, such as cache memory for DSP, bit-slice, or multi- Fully asynchronous operation processor designs. Each port has independent control pins chip enable (CE), write Automatic power down enable (R/W), and output enable (OE). Two flags are provided Master CY7C130/130A/CY7C131/131A easily expands data on each port, BUSY and INT. BUSY signals that the port is trying bus width to 16 or more bits using slave CY7C140/CY7C141 to access the same location currently being accessed by the other port. INT is an interrupt flag indicating that data is placed BUSY output flag on CY7C130/130A/CY7C131/131A BUSY in a unique location (3FF for the left port and 3FE for the right input on CY7C140/CY7C141 port). An automatic power down feature is controlled indepen- INT flag for port-to-port communication dently on each port by the chip enable (CE) pins. The CY7C130/130A and CY7C140 are available in 48-pin DIP. Available in 48-pin DIP (CY7C130/130A/140), 52-pin PLCC, The CY7C131/131A and CY7C141 are available in 52-pin 52-pin TQFP PLCC, 52-pin Pb-free PLCC, 52-pin PQFP, and 52-pin Pb-free Pb-free packages available PQFP. Logic Block Diagram R/W L R/W R CE L CE R OE L OE R I/O I/O 7L 7R I/O I/O CONTROL CONTROL I/O I/O 0R 0L 2 BUSY BUSY L R A A 9L 9R MEMORY ADDRESS ADDRESS ARRAY DECODER DECODER A A 0L 0R ARBITRATION LOGIC (7C130/7C131 ONLY) CE CE L R AND INTERRUPT LOGIC OE L OE R R/W R/W L R 3 3 INT INT L R Notes 1. CY7C130 and CY7C130A are functionally identical CY7C131 and CY7C131A are functionally identical. 2. CY7C130/130A/CY7C131/131A (Master): BUSY is open drain output and requires pull-up resistor. CY7C140/CY7C141 (Slave): BUSY is input. 3. Open drain outputs: pull-up resistor required. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document : 38-06002 Rev. *E Revised December 09, 2008 + Feedback CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Pin Configurations Figure 1. Pin Diagram - DIP (Top View) CE 48 V 1 CC L R/W 47 CE L 2 R BUSY 46 R/W L R 3 BUSY INT 45 R L 4 OE 44 INT 5 R L A 0L 43 OE 6 R A 42 A 0R 1L 7 A 41 A 2L 1R 8 A 40 A 3L 2R 9 A 39 A 4L 10 3R A 5L A 11 38 4R A A 12 37 5R 6L 7C130 A A 13 7C140 36 7L 6R A 8L 14 35 A 7R A 15 A 9L 34 8R I/O 16 A 0L 33 9R I/O 1L 17 I/O 32 7R I/O 2L 18 31 I/O 6R I/O 3L 19 30 I/O 5R I/O I/O 4L 20 29 4R I/O 21 28 I/O 5L 3R I/O I/O 22 27 2R 6L I/O I/O 23 26 7L 1R 24 25 I/O GND 0R Figure 2. Pin Diagram - PLCC (Top View) Figure 3. Pin Diagram - PQFP (Top View) 7 6 5 4 3 2 1 52 51 50 49 48 47 A 1L 8 46 OE R A 2L A 9 45 0R A 3L A 52 5150 49 48 47 4645 44 43 42 41 40 10 44 1R A A 1L 1 39 OE 4L 11 43 A R 2R A A A 2L 2 38 5L A 0R 12 42 3R A A A 3L 3 37 1R 6L 13 41 A 4R 7C131 A A A 7L A 4L 4 36 2R 14 40 5R 7C141 A A A 5L 5 35 3R 8L A 15 39 6R A A A 4R A 6L 6 34 9L 16 38 7R 7C131 A A 5R I/O 7L 7 33 0L A 7C141 17 37 8R A A 8L I/O 8 32 6R 1L 18 36 A 9R A A I/O 9L 9 31 7R 2L 19 35 NC I/O A 0L I/O 10 30 8R 3L 20 34 I/O 7R I/O A 2122 23 24 25 26 27 28 29 30 31 32 33 1L 11 29 9R I/O NC 2L 12 28 I/O 3L I/O 7R 13 27 1415 16 17 18 19 20 21 22 23 24 25 26 Document : 38-06002 Rev. *E Page 2 of 19 + Feedback I/O A 4L 0L I/O 5L OE L I/O NC 6L I/O INT 7L L NC BUSY L GND R/W L I/O CE 0R L V I/O CC 1R CE I/O R 2R R/W I/O R 3R I/O BUSY 4R R I/O INT 5R R I/O NC 6R A I/O 0L 4L I/O OE 5L L NC I/O 6L INT I/O L 7L BUSY NC L R/W GND L CE I/O L 0R V CC I/O 1R CE R I/O 2R R/W R I/O 3R I/O BUSY 4R R I/O INT 5R R NC I/O 6R