CY7C1311KV18/CY7C1911KV18
CY7C1313KV18/CY7C1315KV18
18-Mbit QDR II SRAM
Four-Word Burst Architecture
18-Mbit QDR II SRAM Four-Word Burst Architecture
Features Configurations
Separate independent read and write data ports CY7C1311KV18 2 M 8
Supports concurrent transactions
CY7C1911KV18 2 M 9
333-MHz clock for high bandwidth
CY7C1313KV18 1 M 18
CY7C1315KV18 512 K 36
Four-word burst for reducing address bus frequency
Double data rate (DDR) interfaces on both read and write ports
Functional Description
(data transferred at 666 MHz) at 333 MHz
The CY7C1311KV18, CY7C1911KV18, CY7C1313KV18, and
Two input clocks (K and K) for precise DDR timing
CY7C1315KV18 are 1.8 V Synchronous Pipelined SRAMs,
SRAM uses rising edges only
equipped with QDR II architecture. QDR II architecture consists
of two separate ports: the read port and the write port to access
Two Input Clocks for Output Data (C and C) to minimize Clock
the memory array. The read port has dedicated data outputs to
skew and flight time mismatches
support read operations and the write port has dedicated data
Echo clocks (CQ and CQ) simplify data capture in high speed
inputs to support write operations. QDR II architecture has
systems
separate data inputs and data outputs to completely eliminate
the need to turnaround the data bus that exists with common
Single multiplexed address input bus latches address inputs
I/O devices. Each port can be accessed through a common
for read and write ports
address bus. Addresses for read and write addresses are
Separate port selects for depth expansion
latched on alternate rising edges of the input (K) clock. Accesses
to the QDR II read and write ports are independent of one
Synchronous internally self-timed writes
another. To maximize data throughput, both read and write ports
are equipped with DDR interfaces. Each address location is
QDR II operates with 1.5 cycle read latency when DOFF is
associated with four 8-bit words (CY7C1311KV18), 9-bit words
asserted HIGH
(CY7C1911KV18), 18-bit words (CY7C1313KV18), or 36-bit
Operates similar to QDR I device with 1 cycle read latency when
words (CY7C1315KV18) that burst sequentially into or out of the
DOFF is asserted LOW
device. Because data can be transferred into and out of the
device on every rising edge of both input clocks (K and K and C
Available in 8, 9, 18, and 36 configurations
and C), memory bandwidth is maximized while simplifying
Full data coherency, providing most current data
system design by eliminating bus turnarounds.
Depth expansion is accomplished with port selects, which
Core V = 1.8 V (0.1 V); I/O V = 1.4 V to V
DD DDQ DD
enables each port to operate independently.
Supports both 1.5 V and 1.8 V I/O supply
All synchronous inputs pass through input registers controlled by
Available in 165-ball FBGA package (13 15 1.4 mm)
the K or K input clocks. All data outputs pass through output
Offered in both Pb-free and non Pb-free packages registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
Variable drive HSTL output buffers
synchronous self-timed write circuitry.
JTAG 1149.1 compatible test access port
PLL for accurate data placement
Selection Guide
Description 333 MHz 300 MHz 250 MHz Unit
Maximum operating frequency 333 300 250 MHz
Maximum operating current 8 Not Offered Not Offered 430 mA
9 520 490 430
18 530 500 440
36 730 670 590
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 001-58904 Rev. *G Revised May 9, 2014512 K x 9 Array
512 K x 8 Array
512 K x 9 Array
512 K x 8 Array
512 K x 9 Array
512 K x 8 Array
512 K x 9 Array
512 K x 8 Array
CY7C1311KV18/CY7C1911KV18
CY7C1313KV18/CY7C1315KV18
Logic Block Diagram CY7C1311KV18
8
D
[7:0]
Write Write Write Write
19
Address
A
Reg Reg Reg Reg
(18:0)
Register
19 Address
A
(18:0)
Register
RPS
K
Control
CLK
K
Logic
Gen. C
DOFF
Read Data Reg.
C
CQ
32
V
16
REF
8 CQ
Reg. Reg.
Control
WPS 8
Logic
8
8
16
NWS Q
Reg.
[1:0] [7:0]
8
Logic Block Diagram CY7C1911KV18
9
D
[8:0]
Write Write Write Write
19
Address
A
Reg Reg Reg Reg
(18:0)
Register
19 Address
A
(18:0)
Register
RPS
K
Control
CLK
K
Logic
Gen. C
DOFF
Read Data Reg.
C
CQ
36
V
18
REF
9 CQ
Reg. Reg.
Control
WPS 9
Logic
9
9
18
BWS Q
Reg.
[0] [8:0]
9
Document Number: 001-58904 Rev. *G Page 2 of 32
Write Add. Decode Write Add. Decode
Read Add. Decode Read Add. Decode