CY7C1318KV18/CY7C1320KV18
18-Mbit DDR II SRAM
Two-Word Burst Architecture
18-Mbit DDR II SRAM Two-Word Burst Architecture
Features Configurations
18-Mbit density (1M 18, 512K 36) CY7C1318KV18 1M 18
CY7C1320KV18 512K 36
333-MHz clock for high bandwidth
Two-word burst for reducing address bus frequency
Functional Description
Double data rate (DDR) interfaces (data transferred at
The CY7C1318KV18, and CY7C1320KV18 are 1.8 V
666 MHz) at 333 MHz
synchronous pipelined SRAM equipped with DDR II architecture.
The DDR II consists of an SRAM core with advanced
Two input clocks (K and K) for precise DDR timing
synchronous peripheral circuitry and a 1-bit burst counter.
SRAM uses rising edges only
Addresses for read and write are latched on alternate rising
Two input clocks for output data (C and C) to minimize clock
edges of the input (K) clock. Write data is registered on the rising
skew and flight time mismatches
edges of both K and K. Read data is driven on the rising edges
of C and C if provided, or on the rising edge of K and K if C/C are
Echo clocks (CQ and CQ) simplify data capture in high-speed
not provided. On CY7C1318KV18 and CY7C1320KV18, the
systems
burst counter takes in the least significant bit of the external
Synchronous internally self-timed writes address and bursts two 18-bit words in the case of
CY7C1318KV18 and two 36-bit words in the case of
DDR II operates with 1.5 cycle read latency when DOFF is
CY7C1320KV18 sequentially into or out of the device.
asserted HIGH
Asynchronous inputs include an output impedance matching
Operates similar to DDR-I device with 1 cycle read latency
input (ZQ). Synchronous data outputs (Q, sharing the same
when DOFF is asserted LOW
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
1.8 V core power supply with HSTL inputs and outputs
capturing data from each individual DDR SRAM in the system
Variable drive HSTL output buffers design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.
Expanded HSTL output voltage (1.4 VV )
DD
All synchronous inputs pass through input registers controlled by
Supports both 1.5 V and 1.8 V I/O supply
the K or K input clocks. All data outputs pass through output
Available in 165-ball FBGA package (13 15 1.4 mm)
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
Offered in both Pb-free and non Pb-free packages
synchronous self-timed write circuitry.
JTAG 1149.1 compatible test access port
For a complete list of related documentation, click here.
Phase locked loop (PLL) for accurate data placement
Selection Guide
Description 333 MHz 300 MHz 250 MHz Unit
Maximum operating frequency 333 300 250 MHz
Maximum operating current 18 450 430 380 mA
36 560 520 460
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 001-58905 Rev. *K Revised February 5, 2016512K x 18 Array 256K x 36 Array
256K x 36 Array
512K x 18 Array
CY7C1318KV18/CY7C1320KV18
Logic Block Diagram CY7C1318KV18
Burst
A0
Logic
Write
Write
20 19
A
Reg
(19:0) Reg
A
Address
(19:1)
Register
18
LD
K
Output
CLK R/W
Logic
K
Gen.
Control
C
DOFF
Read Data Reg.
C
36
V CQ
REF 18
18
Reg. Reg.
Control
CQ
R/W
Logic
18
18
BWS DQ
[1:0] 18
Reg. [17:0]
Logic Block Diagram CY7C1320KV18
Burst
A0
Logic
Write Write
19 18
A
Reg Reg
(18:0)
A
Address
(18:1)
Register
36
LD
K
Output
CLK R/W
K Logic
Gen.
Control
C
DOFF Read Data Reg.
C
72
CQ
V
36
REF
36
Reg. Reg.
Control
CQ
R/W
Logic
36
36
BWS DQ
36
[3:0] Reg. [35:0]
Document Number: 001-58905 Rev. *K Page 2 of 32
Write Add. Decode
Write Add. Decode
Read Add. Decode Read Add. Decode