CY7C131E, CY7C131AE CY7C136E, CY7C136AE 1 K / 2 K 8 Dual-port Static RAM 1 K / 2 K 8 Dual-port Static RAM Features Functional Description True dual-ported memory cells, which allow simultaneous CY7C131E / CY7C131AE / CY7C136E / CY7C136AE are reads of the same memory location high-speed, low-power CMOS 1 K / 2 K 8 dual-port static RAMs. Two ports are provided permitting independent access to 1 K / 2 K 8 organization any location in memory. The CY7C131E / CY7C131AE / 0.35 micron complementary metal oxide semiconductor CY7C136E / CY7C136AE can be used as a standalone dual-port (CMOS) for optimum speed and power static RAM. It is the solution to applications requiring shared or buffered data, such as cache memory for DSP, bit-slice, or multi- High speed access: 15 ns processor designs. Low operating power: I = 110 mA (typical), CC Each port has independent control pins chip enable (CE), write Standby: I = 0.05 mA (typical) SB3 enable (R/W), and output enable (OE). Two flags are provided Fully asynchronous operation on each port, BUSY and INT. The BUSY flag signals that the port Automatic power-down is trying to access the same location, which is currently being accessed by the other port. The INT is an interrupt flag indicating BUSY output flag to indicate access to the same location by 1 that data is placed in a unique location . The BUSY and INT both ports flags are push pull outputs. An automatic power-down feature is INT flag for port-to-port communication controlled independently on each port by the chip enable (CE) pins. Available in 52-pin plastic leaded chip carrier (PLCC), 52-pin plastic quad flat package (PQFP) The CY7C131E / CY7C131AE / CY7C136E / CY7C136AE are available in 52-pin Pb-free PLCC and 52-pin Pb-free PQFP. Pb-free packages available Logic Block Diagram R/W L R/W R CE L CE R OE L OE R I/O 7L I/O 7R I/O I/O CONTROL CONTROL I/O I/O 0L 0R 2 2 BUSY BUSY L R A A 9/10L 9/10R MEMORY ADDR ADDR 4 4 DECODER ARRAY DECODER A A 0L 0R 7C131E/7C131AE/ ARBITRATION 7C136E/7C136AE LOGIC ARBITRATION LOGIC (7C130/7C131 ONLY) CE L CE R AND INTERRUPT LOGIC OE L INTERRUPT LOGIC OE R R/W R/W L R 3 3 INT INT L R Notes 1. Unique location used by interrupt flag: 1 K 8: Left port reads from 3FE, Right port reads from 3FF 2 K 8: Left port reads from 7FE, Right port reads from 7FF. 2. BUSY is a push-pull output. No pull-up resistor required. 3. INT: push-pull output. No pull-up resistor required. 4. 1 K 8: A0A9, 2 K 8: A0A10, address lines are for both left and right ports. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-64231 Rev. *D Revised June 15, 2012CY7C131E, CY7C131AE CY7C136E, CY7C136AE Contents Pin Configurations ...........................................................3 Ordering Information ...................................................... 15 Pin Definitions ..................................................................3 Ordering Code Definitions ......................................... 15 Selection Guide ................................................................3 Package Diagrams .......................................................... 16 Maximum Ratings............................................................. 4 Acronyms ........................................................................17 Operating Range............................................................... 4 Document Conventions ................................................. 17 Electrical Characteristics .................................................4 Units of Measure ....................................................... 17 Capacitance ......................................................................5 Document History Page ................................................. 18 AC Test Loads and Waveforms .......................................5 Sales, Solutions, and Legal Information ...................... 19 Switching Characteristics ................................................6 Worldwide Sales and Design Support ....................... 19 Switching Characteristics ................................................8 Products ....................................................................19 Switching Waveforms ....................................................10 PSoC Solutions ......................................................... 19 Document Number: 001-64231 Rev. *D Page 2 of 19