CY7C1327G 4-Mbit (256K 18) Pipelined Sync SRAM 4-Mbit (256K 18) Pipelined Sync SRAM Features Functional Description Registered inputs and outputs for pipelined operation The CY7C1327G SRAM integrates 256K 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter 256K 18 common I/O Architecture for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input 3.3 V core power supply (V ) DD (CLK). The synchronous inputs include all addresses, all data 2.5 V I/O power supply (V ) DDQ inputs, address-pipelining chip enable (CE ), depth-expansion 1 chip enables (CE and CE ), burst control inputs (ADSC, ADSP, 2 3 Fast clock-to-output times and ADV), write enables (BW , and BWE), and global write A:B 3.5 ns (for 166-MHz device) (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin. Provide high performance 3-1-1-1 access rate Addresses and chip enables are registered at rising edge of User-selectable burst counter supporting Intel Pentium clock when either address strobe processor (ADSP) or address interleaved or linear burst sequences strobe controller (ADSC) are active. Subsequent burst Separate processor and controller address strobes addresses can be internally generated as controlled by the advance pin (ADV). Synchronous self-timed writes Address, data inputs, and write controls are registered on-chip Asynchronous output enable to initiate a self-timed Write cycle.This part supports byte write operations (see Pin Descriptions and Truth Table for further Offered in Pb-free 100-pin TQFP package details). Write cycles can be one to two bytes wide as controlled ZZ sleep mode option by the byte write control inputs. GW when active causes all LOW bytes to be written. The CY7C1327G operates from a +3.3 V core power supply while all outputs also operate with a +3.3 V or a +2.5 V supply. All inputs and outputs are JEDEC-standard JESD8-5- compatible. For a complete list of related documentation, click here. Logic Block ADDRESS A0, A1, A REGISTER A 1:0 2 MODE ADV Q1 BURST CLK COUNTER AND LOGIC CLR Q0 ADSC ADSP DQ B,DQP B DQ B,DQP B WRITE DRIVER WRITE REGISTER OUTPUT BW B DQs SENSE OUTPUT MEMORY BUFFERS DQP A AMPS ARRAY REGISTERS DQP B DQ A, DQP A E DQ A, DQP A WRITE DRIVER BW A WRITE REGISTER BWE INPUT GW REGISTERS ENABLE CE 1 PIPELINED REGISTER CE2 ENABLE CE3 OE SLEEP ZZ CONTROL Errata: For information on silicon errata, seeErrat on page 21. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05519 Rev. *Q Revised November 4, 2016CY7C1327G Contents Selection Guide ................................................................3 AC Test Loads and Waveforms ..................................... 12 Pin Configurations ...........................................................3 Switching Characteristics .............................................. 13 Pin Definitions ..................................................................4 Switching Waveforms .................................................... 14 Functional Overview ........................................................6 Ordering Information ...................................................... 18 Single Read Accesses ................................................6 Ordering Code Definitions ......................................... 18 Single Write Accesses Initiated by ADSP ...................6 Package Diagrams .......................................................... 19 Single Write Accesses Initiated by ADSC ...................6 Acronyms ........................................................................20 Burst Sequences .........................................................6 Document Conventions ................................................. 20 Sleep Mode .................................................................6 Units of Measure ....................................................... 20 Interleaved Burst Address Table .................................7 Errata ...............................................................................21 Linear Burst Address Table .........................................7 Part Numbers Affected .............................................. 21 ZZ Mode Electrical Characteristics ..............................7 Product Status ........................................................... 21 Truth Table ........................................................................8 Ram9 Sync ZZ Pin Issues Errata Summary .............. 21 Truth Table for Read/Write ..............................................9 Document History Page ................................................. 22 Maximum Ratings ...........................................................10 Sales, Solutions, and Legal Information ...................... 24 Operating Range .............................................................10 Worldwide Sales and Design Support ....................... 24 Neutron Soft Error Immunity .........................................10 Products ....................................................................24 Electrical Characteristics ...............................................10 PSoCSolutions .......................................................24 Capacitance ....................................................................11 Cypress Developer Community ................................. 24 Thermal Resistance ........................................................11 Technical Support ..................................................... 24 Document Number: 38-05519 Rev. *Q Page 2 of 24