CY7C1329H 2-Mbit (64 K 32) Pipelined Sync SRAM 2-Mbit (64 K 32) Pipelined Sync SRAM Features Functional Description Registered inputs and outputs for pipelined operation The CY7C1329H SRAM integrates 64 K 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter 64 K 32 common I/O architecture for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input 3.3 V core power supply (CLK). The synchronous inputs include all addresses, all data 2.5 V/3.3 V I/O operation inputs, address-pipelining Chip Enable (CE ), depth-expansion 1 Chip Enables (CE and CE ), Burst Control inputs (ADSC, 2 3 Fast clock-to-output times ADSP, ADV), Write Enables (BW and BWE), and Global and A:D 4.0 ns (for 133-MHz device) Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Provide high-performance 3-1-1-1 access rate Addresses and chip enables are registered at rising edge of User-selectable burst counter supporting Intel Pentium clock when either Address Strobe Processor (ADSP) or Address interleaved or linear burst sequences Strobe Controller (ADSC) are active. Subsequent burst Separate processor and controller address strobes addresses can be internally generated as controlled by the Advance pin (ADV). Synchronous self-timed write Address, data inputs, and write controls are registered on-chip Asynchronous output enable to initiate a self-timed Write cycle. This part supports Byte Write operations (see Pin Definitions on page 4 and Truth Table on Offered in JEDEC-standard lead-free 100-pin TQFP package page 7 for further details). Write cycles can be one to four bytes ZZ Sleep Mode Option wide as controlled by the Byte Write control inputs. GW when active LOW causes all bytes to be written. The CY7C1329H operates from a +3.3 V core power supply while all outputs operate with either a +2.5 V or +3.3 V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Logic Block Diagram A0, A1, A ADDRESS REGISTER 2 A 1:0 MODE Q1 ADV BURST CLK COUNTER CLR AND Q0 LOGIC ADSC ADSP DQD DQD BYTE BYTE BWD WRITE REGISTER WRITE DRIVER DQC DQC BYTE BWC BYTE OUTPUT WRITE DRIVER WRITE REGISTER OUTPUT MEMORY SENSE DQs BUFFERS ARRAY REGISTERS AMPS DQB E DQB BYTE BYTE BWB WRITE DRIVER WRITE REGISTER DQA DQA BYTE BWA BYTE WRITE DRIVER WRITE REGISTER BWE INPUT GW REGISTERS ENABLE PIPELINED CE1 REGISTER ENABLE CE2 CE3 OE SLEEP ZZ CONTROL Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05673 Rev. *G Revised July 30, 2013CY7C1329H Contents Selection Guide ................................................................3 Thermal Resistance ........................................................ 10 Pin Configurations ...........................................................3 AC Test Loads and Waveforms ..................................... 10 Pin Definitions ..................................................................4 Switching Characteristics .............................................. 11 Functional Overview ........................................................5 Switching Waveforms .................................................... 12 Single Read Accesses ................................................5 Ordering Information ...................................................... 16 Single Write Accesses Initiated by ADSP ...................5 Ordering Code Definitions ......................................... 16 Single Write Accesses Initiated by ADSC ...................5 Package Diagram ............................................................ 17 Burst Sequences .........................................................5 Acronyms ........................................................................18 Sleep Mode .................................................................5 Document Conventions ................................................. 18 Interleaved Burst Address Table .................................6 Units of Measure ....................................................... 18 Linear Burst Address Table .........................................6 Document History Page ................................................. 19 ZZ Mode Electrical Characteristics ..............................6 Sales, Solutions, and Legal Information ...................... 20 Truth Table ........................................................................7 Worldwide Sales and Design Support ....................... 20 Truth Table for Read/Write ..............................................8 Products ....................................................................20 Maximum Ratings .............................................................9 PSoC Solutions ...................................................... 20 Operating Range ...............................................................9 Cypress Developer Community ................................. 20 Electrical Characteristics .................................................9 Technical Support ..................................................... 20 Capacitance ....................................................................10 Document Number: 38-05673 Rev. *G Page 2 of 20