CY7C1338G 4-Mbit (128K 32) Flow-Through Sync SRAM 4-Mbit (128K 32) Flow-Through Sync SRAM first address in a burst and increments the address automatically Features for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input 128K 32 common I/O (CLK). The synchronous inputs include all addresses, all data 3.3 V core power supply (V ) DD inputs, address-pipelining chip enable (CE ), depth-expansion 1 chip enables (CE and CE ), burst control inputs (ADSC, ADSP, 2 3 2.5 V or 3.3 V I/O supply (V ) DDQ and ADV), write enables (BW , and BWE), and global write A:D Fast clock-to-output times (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin. 8.0 ns (100-MHz version) The CY7C1338G allows either interleaved or linear burst Provide high-performance 2-1-1-1 access rate sequences, selected by the MODE input pin. A HIGH selects an User-selectable burst counter supporting Intel Pentium interleaved burst sequence, while a LOW selects a linear burst interleaved or linear burst sequences sequence. Burst accesses can be initiated with the processor address strobe (ADSP) or the cache controller address strobe Separate processor and controller address strobes (ADSC) inputs. Address advancement is controlled by the Synchronous self-timed write address advancement (ADV) input. Addresses and chip enables are registered at rising edge of Asynchronous output enable clock when either address strobe processor (ADSP) or address Offered in Pb-free 100-pin TQFP package strobe controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the ZZ sleep mode option advance pin (ADV). Functional Description The CY7C1338G operates from a +3.3 V core power supply while all outputs may operate with either a +2.5 or +3.3 V supply. The CY7C1338G is a 128K 32 synchronous cache RAM All inputs and outputs are JEDEC-standard designed to interface with high-speed microprocessors with JESD8-5-compatible. minimum glue logic. Maximum access delay from clock rise is For a complete list of related documentation, click here. 8.0 ns (100-MHz version). A 2-bit on-chip counter captures the Logic Block Diagram ADDRESS A0, A1, A REGISTER A 1:0 MODE ADV Q1 BURST CLK COUNTER AND LOGIC Q0 CLR ADSC ADSP DQD BYTE DQD BYTE WRITE REGISTER BWD WRITE REGISTER DQC BYTE DQC BYTE WRITE REGISTER BWC WRITE REGISTER OUTPUT MEMORY SENSE DQs BUFFERS ARRAY DQB BYTE AMPS DQB BYTE WRITE REGISTER BWB WRITE REGISTER DQA BYTE DQA BYTE WRITE REGISTER BWA WRITE REGISTER BWE INPUT GW REGISTERS ENABLE CE1 REGISTER CE2 CE3 OE SLEEP ZZ CONTROL Errata: For information on silicon errata, seeErrat on page 20. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05521 Rev. *P Revised November 8, 2016CY7C1338G Contents Selection Guide ................................................................3 Switching Characteristics .............................................. 12 Pin Configurations ...........................................................3 Timing Diagrams ............................................................ 13 Pin Definitions ..................................................................4 Ordering Information ...................................................... 17 Functional Overview ........................................................6 Ordering Code Definitions ......................................... 17 Single Read Accesses ................................................6 Package Diagrams .......................................................... 18 Single Write Accesses Initiated by ADSP ...................6 Acronyms ........................................................................19 Single Write Accesses Initiated by ADSC ...................6 Document Conventions ................................................. 19 Burst Sequences .........................................................6 Units of Measure ....................................................... 19 Sleep Mode .................................................................6 Errata ...............................................................................20 Interleaved Burst Address Table .................................7 Part Numbers Affected .............................................. 20 Linear Burst Address Table .........................................7 Product Status ........................................................... 20 ZZ Mode Electrical Characteristics ..............................7 Ram9 Sync ZZ Pin Issues Errata Summary .............. 20 Truth Table ........................................................................8 Document History Page ................................................. 21 Partial Truth Table for Read/Write ..................................9 Sales, Solutions, and Legal Information ...................... 23 Maximum Ratings ...........................................................10 Worldwide Sales and Design Support ....................... 23 Operating Range .............................................................10 Products ....................................................................23 Electrical Characteristics ...............................................10 PSoCSolutions .......................................................23 Capacitance ....................................................................11 Cypress Developer Community ................................. 23 Thermal Resistance ........................................................11 Technical Support ..................................................... 23 AC Test Loads and Waveforms .....................................11 Document Number: 38-05521 Rev. *P Page 2 of 23