CY7C1339G 4-Mbit (128K 32) Pipelined Sync SRAM 4-Mbit (128K 32) Pipelined Sync SRAM Features Functional Description Registered inputs and outputs for pipelined operation The CY7C1339G SRAM integrates 128K 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter 128K 32 common I/O architecture for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input 3.3 V core power supply (V ) DD (CLK). The synchronous inputs include all addresses, all data 2.5 V/3.3 V I/O power supply (V ) DDQ inputs, address-pipelining chip enable (CE ), depth-expansion 1 chip enables (CE and CE ), burst control inputs (ADSC, ADSP, 2 3 Fast clock-to-output times ADV), write enables (BW , and BWE), and global write and A:D 4.0 ns (for 133-MHz device) ( ). Asynchronous inputs include the output enable (OE) and GW the ZZ pin. Provide high-performance 3-1-1-1 access rate Addresses and chip enables are registered at rising edge of User-selectable burst counter supporting Intel Pentium clock when either address strobe processor (ADSP) or address interleaved or linear burst sequences strobe controller (ADSC) are active. Subsequent burst Separate processor and controller address strobes addresses can be internally generated as controlled by the advance pin (ADV). Synchronous self-timed writes Address, data inputs, and write controls are registered on-chip Asynchronous output enable to initiate a self-timed write cycle.This part supports byte write operations (see Pin Descriptions and Truth Table for further Available in Pb-free 100-pin TQFP package details). Write cycles can be one to four bytes wide as controlled ZZ sleep mode option by the byte write control inputs. GW when active LOW causes all bytes to be written. The CY7C1339G operates from a +3.3 V core power supply while all outputs may operate with either a +2.5 or +3.3 V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. For a complete list of related documentation, click here. Logic Block Diagram A0, A1, A ADDRESS REGISTER 2 A 1:0 MODE Q1 ADV BURST CLK COUNTER CLR AND Q0 LOGIC ADSC ADSP DQ D DQ D BYTE BYTE BW D WRITE REGISTER WRITE DRIVER DQ C DQ C BYTE BYTE BW C OUTPUT WRITE REGISTER WRITE DRIVER OUTPUT MEMORY SENSE DQ s BUFFERS ARRAY REGISTERS AMPS DQ B E DQ B BYTE BYTE BW B WRITE DRIVER WRITE REGISTER DQ A DQ A BYTE BW A BYTE WRITE DRIVER WRITE REGISTER BW E INPUT GW REGISTERS ENABLE PIPELINED CE1 REGISTER ENABLE CE2 CE3 OE SLEEP ZZ CONTROL Errata: For information on silicon errata, seeErrat on page 20. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05520 Rev. *R Revised November 8, 2016CY7C1339G Contents Selection Guide ................................................................3 Switching Characteristics .............................................. 12 Pin Configurations ...........................................................3 Switching Waveforms .................................................... 13 Pin Definitions ..................................................................4 Ordering Information ...................................................... 17 Functional Overview ........................................................6 Ordering Code Definitions ......................................... 17 Single Read Accesses ................................................6 Package Diagrams .......................................................... 18 Single Write Accesses Initiated by ADSP ...................6 Acronyms ........................................................................19 Single Write Accesses Initiated by ADSC ...................6 Document Conventions ................................................. 19 Burst Sequences .........................................................6 Units of Measure ....................................................... 19 Sleep Mode .................................................................6 Errata ...............................................................................20 Interleaved Burst Address Table .................................7 Part Numbers Affected .............................................. 20 Linear Burst Address Table .........................................7 Product Status ........................................................... 20 ZZ Mode Electrical Characteristics ..............................7 Ram9 Sync ZZ Pin Issues Errata Summary .............. 20 Truth Table ........................................................................8 Document History Page ................................................. 21 Partial Truth Table for Read/Write ..................................9 Sales, Solutions, and Legal Information ...................... 23 Maximum Ratings ...........................................................10 Worldwide Sales and Design Support ....................... 23 Operating Range .............................................................10 Products ....................................................................23 Electrical Characteristics ...............................................10 PSoCSolutions .......................................................23 Capacitance ....................................................................11 Cypress Developer Community ................................. 23 Thermal Resistance ........................................................11 Technical Support ..................................................... 23 AC Test Loads and Waveforms .....................................11 Document Number: 38-05520 Rev. *R Page 2 of 23