CY7C1345G 4-Mbit (128K 36) Flow-Through Sync SRAM 4-Mbit (128K 36) Flow-Through Sync SRAM Features Functional Description 128K 36 common I/O The CY7C1345G is a 128K 36 synchronous cache RAM designed to interface with high speed microprocessors with 3.3 V core power supply (V ) DD minimum glue logic. The maximum access delay from clock rise is 8.0 ns (100 MHz version). A 2-bit on-chip counter captures the 2.5 V or 3.3 V I/O supply (V ) DDQ first address in a burst and increments the address automatically Fast clock-to-output times for the rest of the burst access. All synchronous inputs are gated 8.0 ns (100 MHz version) by registers controlled by a positive edge triggered Clock Input (CLK). The synchronous inputs include all addresses, all data Provide high performance 2-1-1-1 access rate inputs, address pipelining chip enable (CE ), depth expansion 1 chip enables (CE and CE ), burst control inputs (ADSC, ADSP, User selectable burst counter supporting Intel Pentium 2 3 ADV), write enables BW and BWE), and global write interleaved or linear burst sequences and ( , x (GW). Asynchronous inputs include the output enable (OE) and Separate processor and controller address strobes the ZZ pin. Synchronous self timed write The CY7C1345G enables either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an Asynchronous output enable interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses are initiated with the processor Available in Pb-free 100-pin TQFP package address strobe (ADSP) or the cache controller address strobe ZZ sleep mode option (ADSC) inputs. Addresses and chip enables are registered at rising edge of clock when either address strobe processor (ADSP) or address strobe controller ( ) is active. Subsequent burst addresses ADSC are internally generated as controlled by the Advance pin (ADV). The CY7C1345G operates from a +3.3 V core power supply while all outputs operate with either a +2.5 or +3.3 V supply. All inputs and outputs are JEDEC standard JESD8-5 compatible. For a complete list of related documentation, click here. Selection Guide Description 100 MHz Unit Maximum access time 8.0 ns Maximum operating current 205 mA Maximum standby current 40 mA Errata: For information on silicon errata, see Errata on page 22. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05517 Rev. *P Revised November 7, 2016CY7C1345G Logic Block Diagram ADDRESS A0, A1, A REGISTER A 1:0 MODE ADV Q1 BURST CLK COUNTER AND LOGIC Q0 CLR ADSC ADSP DQ D, DQP D DQ D, DQP D BYTE BW D BYTEBYTE WRITE REGISTER WRITE REGISTERWRITE REGISTER DQ C, DQP C DQ C, DQP C BW C BYTE BYTE WRITE REGISTER WRITE REGISTER OUTPUT DQ s MEMORY SENSE BUFFERS ARRAY DQP A DQ B, DQP B AMPS DQ B, DQP B DQP B BYTE BW B DQP C BYTE WRITE REGISTER WRITE REGISTER DQP D DQ A, DQP A BYTE DQ A, DQPA BW A BYTE WRITE REGISTER BWE WRITE REGISTER INPUT GW REGISTERS ENABLE CE1 REGISTER CE2 CE3 OE SLEEP ZZ CONTROL Document Number: 38-05517 Rev. *P Page 2 of 25