CY7C1347G-166AXC

Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY7C1347G 4-Mbit (128K 36) Pipelined Sync SRAM 4-Mbit (128K 36) Pipelined Sync SRAM Features Functional Description The CY7C1347G is a 3.3 V, 128K 36 synchronous pipelined Fully registered inputs and outputs for pipelined operation SRAM designed to support zero-wait-state secondary cache 128K 36 common I/O architecture with minimal glue logic. CY7C1347G I/O pins can operate at either the 2.5 V or the 3.3 V level. The I/O pins are 3.3 V tolerant 3.3 V core power supply (V ) DD when V = 2.5 V. All synchronous inputs pass through input DDQ registers controlled by the rising edge of the clock. All data 2.5 V/ 3.3 V I/O power supply (V ) DDQ outputs pass through output registers controlled by the rising Fast clock to output times: 2.6 ns (for 250 MHz device) edge of the clock. Maximum access delay from the clock rise is 2.6 ns (250 MHz device). CY7C1347G supports either the User selectable burst counter supporting Intel Pentium interleaved burst sequence used by the Intel Pentium processor interleaved or linear burst sequences or a linear burst sequence used by processors such as the Separate processor and controller address strobes Power PC. The burst sequence is selected through the MODE pin. Accesses can be initiated by asserting either the address Synchronous self timed writes strobe from processor (ADSP) or the address strobe from controller (ADSC) at clock rise. Address advancement through Asynchronous output enable the burst sequence is controlled by the ADV input. A 2-bit on-chip Offered in Pb-free 100-pin TQFP package wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest ZZ sleep mode option and stop clock option of the burst access. Available in commercial and industrial temperature range Byte write operations are qualified with the four Byte Write Select (BW ) inputs. A global write enable (GW) overrides all byte A:D write inputs and writes data to all four bytes. All writes are conducted with on-chip synchronous self timed write circuitry. Three synchronous chip Selects (CE , CE , CE ) and an 1 2 3 asynchronous output enable (OE) provide for easy bank selection and output tristate control. To provide proper data during depth expansion, OE is masked during the first clock of a read cycle when emerging from a deselected state. For a complete list of related documentation, click here. Selection Guide Description 250 MHz 200 MHz 166 MHz 133 MHz Unit Maximum access time 2.6 2.8 3.5 4.0 ns Maximum operating current 325 265 240 225 mA Maximum CMOS standby current 40 40 40 40 mA Errata: For information on silicon errata, seeErrat on page 22. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05516 Rev. *T Revised March 22, 2019