CY7C1350G 4-Mbit (128 K 36) Pipelined SRAM with NoBL Architecture 4-Mbit (128 K 36) Pipelined SRAM with NoBL Architecture Features Functional Description Pin compatible and functionally equivalent to ZBT devices The CY7C1350G is a 3.3 V, 128 K 36 synchronous-pipelined burst SRAM designed specifically to support unlimited true Internally self-timed output buffer control to eliminate the need back-to-back read/write operations without the insertion of wait to use OE states. The CY7C1350G is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Byte write capability read/write operations with data being transferred on every clock 128 K 36 common I/O architecture cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent write/read 3.3 V power supply (V ) DD transitions. 2.5 V / 3.3 V I/O power supply (V ) DDQ All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output Fast clock-to-output times registers controlled by the rising edge of the clock. The clock 2.8 ns (for 200-MHz device) input is qualified by the clock enable (CEN) signal, which, when Clock enable (CEN) pin to suspend operation deasserted, suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 2.8 ns Synchronous self-timed writes (200-MHz device). Asynchronous output enable (OE) Write operations are controlled by the four byte write select (BW ) and a write enable (WE) input. All writes are conducted A:D Available in Pb-free 100-pin TQFP package, Pb-free and with on-chip synchronous self-timed write circuitry. non Pb-free 119-ball BGA package Three synchronous chip enables (CE , CE , CE ) and an 1 2 3 Burst capability linear or interleaved burst order asynchronous output enable (OE) provide for easy bank selection and output tristate control. In order to avoid bus ZZ sleep mode option contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. Logic Block Diagram ADDRESS A0, A1, A REGISTER 0 A1 A1 D1 Q1 A0 BURST A0 D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O S U D U E T T A P N P U T U S T ADV/LD A T E WRITE REGISTRY R MEMORY AND DATA COHERENCY WRITE E S B DQs BWA ARRAY CONTROL LOGIC G U DRIVERS A T DQPA BWB I F E DQPB BWC M S F BWD E DQPC T E P E R R DQPD S WE R S I S E N E G INPUT INPUT REGISTER 1 E REGISTER 0 E OE READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Errata: For information on silicon errata, seeErrat on page 20. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05524 Rev. *N Revised June 25, 2013CY7C1350G Contents Selection Guide ................................................................3 Switching Characteristics .............................................. 12 Pin Configurations ...........................................................3 Switching Waveforms .................................................... 13 Pin Definitions ..................................................................5 Ordering Information ...................................................... 15 Functional Overview ........................................................6 Ordering Code Definitions ......................................... 15 Single Read Accesses ................................................6 Package Diagrams .......................................................... 16 Burst Read Accesses ..................................................6 Acronyms ........................................................................18 Single Write Accesses .................................................6 Document Conventions ................................................. 18 Burst Write Accesses ..................................................6 Units of Measure ....................................................... 18 Sleep Mode .................................................................6 Errata ...............................................................................19 Interleaved Burst Address Table .................................7 Part Numbers Affected .............................................. 19 Linear Burst Address Table .........................................7 Product Status ........................................................... 19 ZZ Mode Electrical Characteristics ..............................7 Ram9 Sync/NoBL ZZ Pin Issues Errata Summary .... 19 Truth Table ........................................................................8 Document History Page ................................................. 20 Partial Truth Table for Read/Write ..................................9 Sales, Solutions, and Legal Information ...................... 22 Maximum Ratings ...........................................................10 Worldwide Sales and Design Support ....................... 22 Operating Range .............................................................10 Products ....................................................................22 Electrical Characteristics ...............................................10 PSoC Solutions ...................................................... 22 Capacitance ....................................................................11 Cypress Developer Community ................................. 22 Thermal Resistance ........................................................11 Technical Support ..................................................... 22 AC Test Loads and Waveforms .....................................11 Document Number: 38-05524 Rev. *N Page 2 of 22