CY7C135 4K 8 Dual-Port Static RAM 4K 8 Dual-Port Static RAM Features Functional Description True dual-ported memory cells, which allow simultaneous The CY7C135 is a high speed CMOS 4K 8 dual-port static reads of the same memory location RAMs. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in 4K 8 organization memory. Application areas include interprocessor/multiprocessor designs, communications status 0.65 micron CMOS for optimum speed and power buffering, and dual-port video/graphics memory. High speed access: 15 ns Each port has independent control pins: chip enable (CE), read Low operating power: I = 180 mA (max) or write enable (R/W), and output enable (OE). The CY7C135 is CC suited for those systems that do not require on-chip arbitration Fully asynchronous operation or are intolerant of wait states. Therefore, the user must be aware that simultaneous access to a location is possible. An Automatic power down automatic power down feature is controlled independently on Available in 52-pin plastic leaded chip carrier (PLCC) each port by a chip enable (CE) pin. Pb-free packages available The CY7C135 is available in 52-pin PLCC. For a complete list of related documentation, click here. Logic Block Diagram R/W L R/W R CE CE L R OE OE R L I/O 7L I/O 7R I/O I/O CONTROL CONTROL I/O 0L I/O 0R A 11L A 11R ADDRESS ADDRESS MEMORY DECODER DECODER A ARRAY A 0L 0R SEMAPHORE CE L ARBITRATION CE R (7C1342 only) OE L OE R R/W R/W L R (7C1342 only) (7C1342 only) SEM SEM R L Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-06038 Rev. *K Revised November 4, 2016CY7C135 Contents Selection Guide ................................................................3 Ordering Information ...................................................... 11 Pin Configurations ...........................................................3 4K 8 Dual-Port SRAM ............................................ 11 Pin Definitions ..................................................................3 Ordering Code Definitions ......................................... 11 Architecture ......................................................................4 Package Diagram ............................................................ 12 Functional Description .....................................................4 Acronyms ........................................................................13 Write Operation ...........................................................4 Document Conventions ................................................. 13 Read Operation ...........................................................4 Units of Measure ....................................................... 13 Maximum Ratings .............................................................5 Document History Page ................................................. 14 Operating Range ...............................................................5 Sales, Solutions, and Legal Information ...................... 16 Electrical Characteristics .................................................5 Worldwide Sales and Design Support ....................... 16 Capacitance ......................................................................6 Products ....................................................................16 AC Test Loads and Waveforms .......................................6 PSoCSolutions .......................................................16 Switching Characteristics ................................................7 Cypress Developer Community ................................. 16 Switching Waveforms ......................................................8 Technical Support ..................................................... 16 Typical DC and AC Characteristics ..............................10 Document Number: 38-06038 Rev. *K Page 2 of 16