Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY7C1351G 4-Mbit (128K 36) Flow-Through SRAM with NoBL Architecture 4-Mbit (128K 36) Flow-Through SRAM with NoBL Architecture Features Functional Description Can support up to 133 MHz bus operations with zero wait states The CY7C1351G is a 3.3 V, 128K 36 synchronous flow-through burst SRAM designed specifically to support unlimited true Data is transferred on every clock back-to-back read/write operations without the insertion of wait Pin compatible and functionally equivalent to ZBT devices states. The CY7C1351G is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Internally self-timed output buffer control to eliminate the need Read/Write operations with data being transferred on every clock to use OE cycle. This feature dramatically improves the throughput of data Registered inputs for flow-through operation through the SRAM, especially in systems that require frequent write-read transitions. Byte write capability All synchronous inputs pass through input registers controlled by 128K 36 common I/O architecture the rising edge of the clock. The clock input is qualified by the clock enable (CEN) signal, which when deasserted suspends 2.5 V/3.3 V I/O power supply (V ) DDQ operation and extends the previous clock cycle. Maximum Fast clock-to-output times access delay from the clock rise is 6.5 ns (133-MHz device). 6.5 ns (for 133 MHz device) Write operations are controlled by the four byte write select (BW ) and a write enable (WE) input. All writes are conducted Clock enable (CEN) pin to suspend operation A:D with on-chip synchronous self-timed write circuitry. Synchronous self-timed writes Three synchronous chip enables (CE , CE , CE ) and an 1 2 3 Asynchronous output enable asynchronous output enable (OE) provide for easy bank selection and output tristate control. In order to avoid bus Available in Pb-free 100-pin TQFP package contention, the output drivers are synchronously tristated during the data portion of a write sequence. Burst capability linear or interleaved burst order For a complete list of related documentation, click here. Low standby power Selection Guide Description 133 MHz 100 MHz Unit Maximum access time 6.5 8.0 ns Maximum operating current 225 205 mA Maximum CMOS standby current 40 40 mA Errata: For information on silicon errata, seeErrat on page 19. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05513 Rev. *R Revised January 9, 2018