CY7C135, CY7C135A CY7C1342 4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores Features Functional Description 1 True dual-ported memory cells, which allow simultaneous The CY7C135/135A and CY7C1342 are high speed CMOS 4K reads of the same memory location x 8 dual-port static RAMs. The CY7C1342 includes semaphores that provide a means to allocate portions of the dual-port RAM 4K x 8 organization or any shared resource. Two ports are provided permitting independent, asynchronous access for reads and writes to any 0.65 micron CMOS for optimum speed and power location in memory. Application areas include interpro- High speed access: 15 ns cessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Low operating power: I = 160 mA (max) CC Each port has independent control pins: chip enable (CE), read Fully asynchronous operation or write enable (R/W), and output enable (OE). The CY7C135/135A is suited for those systems that do not require Automatic power down on-chip arbitration or are intolerant of wait states. Therefore, the Semaphores included on the 7C1342 to permit software user must be aware that simultaneous access to a location is handshaking between ports possible. Semaphores are offered on the CY7C1342 to assist in arbitrating between ports. The semaphore logic is comprised of Available in 52-pin PLCC eight shared latches. Only one side can control the latch Pb-free packages available (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power down feature is controlled independently on each port by a chip enable (CE) pin or SEM pin (CY7C1342 only). The CY7C135/135A and CY7C1342 are available in 52-pin PLCC. Logic Block Diagram R/W L R/W R CE CE L R OE OE R L I/O 7L I/O 7R I/O I/O CONTROL CONTROL I/O 0L I/O 0R A 11L A 11R ADDRESS ADDRESS MEMORY DECODER DECODER ARRAY A A 0L 0R SEMAPHORE CE CE L ARBITRATION R (7C1342 only) OE OE L R R/W R/W L R (7C1342 only) (7C1342 only) SEM SEM L R Note 1. CY7C135 and CY7C135A are functionally identical Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document : 38-06038 Rev. *D Revised December 09, 2008 + Feedback CY7C135, CY7C135A CY7C1342 Selection Guide 7C135-15 7C135-20 7C135/135A-25 7C135-35 7C135-55 Parameter Unit 7C1342-15 7C1342-20 7C1342-25 7C1342-35 7C1342-55 Maximum Access Time 15 20 25 35 55 ns Maximum Operating Current Commercial 220 190 180 160 160 mA Maximum Standby Current for Commercial 60 50 40 30 30 mA I SB1 Pin Configurations Figure 1. Pin Diagram - CY7C135/135A (Top View) Figure 2. Pin Diagram - CY7C1342 (Top View) 7 6 5 4 3 2 1 52 51 50 49 48 47 7 6 5 4 3 2 1 52 51 50 49 48 47 A OE 1L 8 46 R A 1L OE 8 46 R A 2L A 9 45 0R A 2L A 9 45 0R A 3L A 10 44 1R A 3L 44 A 10 1R A 4L 11 43 A 2R A 4L A 11 43 2R A 5L A 12 42 3R A 5L A 12 42 3R A 6L 13 41 A 7C135/135A 4R A 6L 13 41 A 7C1342 4R A 7L A 14 40 5R A 7L A 14 40 5R A 8L 15 39 A 6R A 8L 15 39 A 6R A A 9L 16 38 7R A 9L A 16 38 7R I/O 0L 17 37 A 8R I/O 0L 17 37 A 8R I/O 1L 18 36 A 9R I/O A 1L 18 36 9R I/O 2L NC 19 35 I/O 2L NC 19 35 I/O 3L 20 34 I/O 7R I/O 3L 20 34 I/O 7R 21 22 23 24 25 26 27 28 29 30 31 32 33 21 22 23 24 25 26 27 28 29 30 31 32 33 Pin Definitions Left Port Right Port Description A A Address Lines 0L11L 0R11R CE CE Chip Enable L R OE OE Output Enable L R R/W R/W Read/Write Enable L R SEM SEM Semaphore Enable. When asserted LOW, allows access to eight semaphores. The three least L R (CY7C1342 (CY7C1342 significant bits of the address lines determines which semaphore to write or read. The I/O pin 0 only) only) is used when writing to a semaphore. Semaphores are requested by writing a 0 into the respective location. Document : 38-06038 Rev. *D Page 2 of 12 + Feedback I/O A 4L 0L I/O 5L OE L I/O A 6L 10L I/O A 7L 11L NC N/C GND R/W L I/O CE 0R L I/O V CC 1R I/O CE 2R R I/O R/W 3R R I/O 4R N/C I/O A 5R 11R I/O A 6R 10R I/O A 4L 0L I/O 5L OE L I/O A 6L 10L I/O A 7L 11L NC SEM L GND R/W L I/O CE 0R L I/O V CC 1R I/O 2R CE R I/O 3R R/W R I/O 4R SEM R I/O A 5R 11R I/O A 6R 10R