CY7C1352G 4-Mbit (256K 18) Pipelined SRAM with NoBL Architecture 4-Mbit (256K 18) Pipelined SRAM with NoBL Architecture Features Functional Description Pin compatible and functionally equivalent to ZBT devices The CY7C1352G is a 3.3 V, 256K 18 synchronous-pipelined burst SRAM designed specifically to support unlimited true Internally self-timed output buffer control to eliminate the need back-to-back read/write operations without the insertion of wait to use OE states. The CY7C1352G is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Byte write capability read/write operations with data being transferred on every clock 256K 18 common I/O architecture cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent write/read 3.3 V core power supply (V ) DD transitions. 2.5 V/3.3 V I/O power supply (V ) DDQ All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output Fast clock-to-output times registers controlled by the rising edge of the clock. The clock 4.0 ns (for 133-MHz device) input is qualified by the clock enable (CEN) signal, which, when Clock enable (CEN) pin to suspend operation deasserted, suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 4.0 ns Synchronous self-timed writes (133-MHz device). Asynchronous output enable (OE) Write operations are controlled by the two byte write select (BW ) and a write enable (WE) input. All writes are conducted A:B Available in Pb-free 100-pin TQFP package with on-chip synchronous self-timed write circuitry. Burst capability linear or interleaved burst order Three synchronous chip enables (CE , CE , CE ) and an 1 2 3 asynchronous output enable (OE) provide for easy bank ZZ sleep mode option and stop clock option selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. For a complete list of related documentation, click here. Selection Guide Description 133 MHz Unit Maximum access time 4.0 ns Maximum operating current 225 mA Maximum CMOS standby current 40 mA Errata: For information on silicon errata, seeErrat on page 19. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05514 Rev. *O Revised November 3, 2016CY7C1352G Logic Block Diagram CY7C1352G ADDRESS A0, A1, A REGISTER 0 A1 A1 D1 Q1 A0 A0 BURST D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O U U T T P S P D U E U A ADV/LD T N T T WRITE REGISTRY S A R MEMORY E B AND DATA COHERENCY DQs BWA WRITE E U ARRAY S CONTROL LOGIC G DRIVERS A F T DQPA I M F BWB E S DQPB P E E T S R R E S I R N WE S G E E INPUT INPUT E E REGISTER 1 REGISTER 0 OE READ LOGIC CE1 CE2 CE3 Sleep ZZ Control Document Number: 38-05514 Rev. *O Page 2 of 22