Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY7C1353G 4-Mbit (256K 18) Flow-Through SRAM with NoBL Architecture 4-Mbit (256K 18) Flow-Through SRAM with NoBL Architecture Features Functional Description Supports up to 100-MHz bus operations with zero wait states The CY7C1353G is a 3.3V, 256K18 synchronous flow-through burst SRAM designed specifically to support Data is transferred on every clock unlimited true back-to-back read/write operations without the Pin compatible and functionally equivalent to ZBT devices insertion of wait states. The CY7C1353G is equipped with the advanced No Bus Latency (NoBL) logic required to enable Internally self timed output buffer control to eliminate the need consecutive read/write operations with data being transferred on to use OE every clock cycle. This feature dramatically improves the Registered inputs for flow-through operation throughput of data through the SRAM, especially in systems that require frequent write-read transitions. Byte write capability All synchronous inputs pass through input registers controlled by 256K 18 common I/O architecture the rising edge of the clock. The clock input is qualified by the clock enable (CEN) signal, which when deasserted suspends 2.5 V/3.3 V I/O power supply (V ) DDQ operation and extends the previous clock cycle. Maximum Fast clock-to-output times access delay from the clock rise is 8.0 ns (100 MHz device). 8.0 ns (for 100 MHz device) Write operations are controlled by the two byte write select (BW ) and a write enable (WE) input. All writes are conducted Clock enable (CEN) pin to suspend operation A:B with on-chip synchronous self timed write circuitry. Synchronous self timed writes Three synchronous chip enables (CE , CE , CE ) and an 1 2 3 Asynchronous output enable asynchronous output enable (OE) provide for easy bank selection and output tri-state control. To avoid bus contention, Available in Pb-free 100-pin TQFP package the output drivers are synchronously tri-stated during the data portion of a write sequence. Burst capability linear or interleaved burst order Low standby power For a complete list of related documentation, click here. Logic Block Diagram ADDRESS A0, A1, A A1 REGISTER A1 D1 Q1 A0 A0 D0 Q0 MODE BURST CE ADV/LD LOGIC CLK C C CEN WRITE ADDRESS REGISTER O U T P D S U A E T T ADV/LD N A S B MEMORY BWA WRITE E U WRITE REGISTRY S ARRAY DQs DRIVERS F BWB T AND DATA COHERENCY DQPA A F E CONTROL LOGIC DQPB M E E P R R S I S WE N E G INPUT E REGISTER OE READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Errata: For information on silicon errata, see Errata on page 16. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05515 Rev. *R Revised March 25, 2019