CY7C1354C CY7C1356C 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture 1 Features Functional Description Pin-compatible and functionally equivalent to ZBT The CY7C1354C and CY7C1356C are 3.3V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Supports 250-MHz bus operations with zero wait states Latency (NoBL) logic, respectively. They are designed to Available speed grades are 250, 200, and 166 MHz support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354C and CY7C1356C are Internally self-timed output buffer control to eliminate equipped with the advanced (NoBL) logic required to enable the need to use asynchronous OE consecutive Read/Write operations with data being trans- Fully registered (inputs and outputs) for pipelined ferred on every clock cycle. This feature dramatically improves operation the throughput of data in systems that require frequent Byte Write capability Write/Read transitions. The CY7C1354C and CY7C1356C are pin compatible and functionally equivalent to ZBT devices. Single 3.3V power supply (V ) DD All synchronous inputs pass through input registers controlled 3.3V or 2.5V I/O power supply (V ) DDQ by the rising edge of the clock. All data outputs pass through Fast clock-to-output times output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, 2.8 ns (for 250-MHz device) which when deasserted suspends operation and extends the Clock Enable (CEN) pin to suspend operation previous clock cycle. Synchronous self-timed writes Write operations are controlled by the Byte Write Selects Available in lead-free 100-Pin TQFP package, lead-free (BW BW for CY7C1354C and BW BW for CY7C1356C) a d a b and non lead-free 119-Ball BGA package and 165-Ball and a Write Enable (WE) input. All writes are conducted with FBGA package on-chip synchronous self-timed write circuitry. IEEE 1149.1 JTAG-Compatible Boundary Scan Three synchronous Chip Enables (CE , CE , CE ) and an 1 2 3 asynchronous Output Enable (OE) provide for easy bank Burst capabilitylinear or interleaved burst order selection and output tri-state control. In order to avoid bus ZZ Sleep Mode option and Stop Clock option contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. Logic Block DiagramCY7C1354C (256K x 36) ADDRESS A0, A1, A REGISTER 0 A1 A1 D1 Q1 A0 A0 BURST D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O S U D U E T T A P N P U T U S T ADV/LD A T E WRITE REGISTRY R MEMORY AND DATA COHERENCY E S B DQs BWa WRITE ARRAY CONTROL LOGIC G U DRIVERS A T DQPa BWb I F BWc E DQPb M S F BWd E DQPc T P E E R R DQPd S WE R I S S E N E G INPUT INPUT REGISTER 1 E REGISTER 0 E OE READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Note: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document : 38-05538 Rev. *G Revised September 14, 2006CY7C1354C CY7C1356C Logic Block DiagramCY7C1356C (512K x 18) ADDRESS A0, A1, A REGISTER 0 A1 A1 D1 Q1 A0 BURST A0 D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O U U T T P S D P U E U ADV/LD A T N T T WRITE REGISTRY S A R MEMORY E B AND DATA COHERENCY WRITE DQs BWa E ARRAY S U CONTROL LOGIC G DRIVERS A F T DQPa I M E F BWb S DQPb P E E T S R R E S I R N WE S G E E INPUT INPUT REGISTER 1 E REGISTER 0 E OE READ LOGIC CE1 CE2 CE3 Sleep ZZ Control Selection Guide 250 MHz 200 MHz 166 MHz Unit Maximum Access Time 2.8 3.2 3.5 ns Maximum Operating Current 250 220 180 mA Maximum CMOS Standby Current 40 40 40 mA Document : 38-05538 Rev. *G Page 2 of 28