CY7C1354C CY7C1356C 9-Mbit (256K 36/512K 18) Pipelined SRAM with NoBL Architecture 9-Mbit (256K 36/512K 18) Pipelined SRAM with NoBL Architecture Features Functional Description 1 Pin-compatible and functionally equivalent to ZBT The CY7C1354C/CY7C1356C are 3.3V, 256K 36/512K 18 synchronous pipelined burst SRAMs with Supports 250 MHz bus operations with zero wait states No Bus Latency (NoBL) logic, respectively. They are Available speed grades are 250, 200, and 166 MHz designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1354C/CY7C1356C Internally self-timed output buffer control to eliminate the need are equipped with the advanced (NoBL) logic required to enable to use asynchronous OE consecutive read/write operations with data being transferred on Fully registered (inputs and outputs) for pipelined operation every clock cycle. This feature greatly improves the throughput of data in systems that require frequent write/read transitions. Byte write capability The CY7C1354C/CY7C1356C are pin compatible and functionally equivalent to ZBT devices. Single 3.3 V power supply (V ) DD All synchronous inputs pass through input registers controlled by 3.3 V or 2.5 V I/O power supply (V ) DDQ the rising edge of the clock. All data outputs pass through output Fast clock-to-output times registers controlled by the rising edge of the clock. The clock input is qualified by the clock enable (CEN) signal, which when 2.8 ns (for 250 MHz device) deasserted suspends operation and extends the previous clock Clock enable (CEN) pin to suspend operation cycle. Synchronous self-timed writes Write operations are controlled by the byte write selects (BW BW for CY7C1354C and BW BW for CY7C1356C) a d a b Available in Pb-free 100-pin TQFP package, Pb-free, and non and a write enable (WE) input. All writes are conducted with Pb-free 119-ball BGA package and 165-ball FBGA package on-chip synchronous self-timed write circuitry. IEEE 1149.1 JTAG-compatible boundary scan Three synchronous chip enables (CE , CE , CE ) and an 1 2 3 asynchronous output enable (OE) provide for easy bank Burst capability linear or interleaved burst order selection and output tristate control. To avoid bus contention, the ZZ sleep mode option and stop clock option output drivers are synchronously tristated during the data portion of a write sequence. For a complete list of related documentation, click here. Selection Guide Description 250 MHz 200 MHz 166 MHz Unit Maximum access time 2.8 3.2 3.5 ns Maximum operating current 250 220 180 mA Maximum CMOS standby current 40 40 40 mA Note 1. For best-practices recommendations, refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05538 Rev. *T Revised March 9, 2018CY7C1354C CY7C1356C Logic Block Diagram CY7C1354C ADDRESS A0, A1, A REGISTER 0 A1 A1 D1 Q1 A0 A0 BURST D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O S U D U E T A T P N P U T U S T ADV/LD A T WRITE REGISTRY E R MEMORY AND DATA COHERENCY E S B DQ s BW a WRITE ARRAY CONTROL LOGIC G U DRIVERS T DQ Pa BW b A I F BW c E DQ Pb M S F BW d T E DQ Pc E P E R R DQ Pd S WE R S I S E N E G INPUT INPUT REGISTER 1 E REGISTER 0 E OE READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Logic Block Diagram CY7C1356C ADDRESS A0, A1, A REGISTER 0 A1 A1 D1 Q1 A0 BURST A0 D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O U U T T P S P D U E A U ADV/LD T N T T WRITE REGISTRY S A R MEMORY E B AND DATA COHERENCY BW a WRITE E DQ s U ARRAY S CONTROL LOGIC G DRIVERS A F DQ Pa T I M F BW b E S DQ Pb P E E T S R R E I S R N WE S G E E INPUT INPUT E E REGISTER 1 REGISTER 0 OE READ LOGIC CE1 CE2 CE3 Sleep ZZ Control Document Number: 38-05538 Rev. *T Page 2 of 36