CY7C1354CV25
CY7C1356CV25
9-Mbit (256 K 36/512 K 18)
Pipelined SRAM with NoBL Architecture
9-Mbit (256 K 36/512 K 18) Pipelined SRAM with NoBL Architecture
Features Functional Description
[1]
Pin-compatible with and functionally equivalent to ZBT The CY7C1354CV25/CY7C1356CV25 are 2.5V,
256 K 36/512 K 18 synchronous pipelined burst SRAMs with
Supports 250-MHz bus operations with zero wait states
No Bus Latency (NoBL logic, respectively. They are
designed to support unlimited true back-to-back read/write
Available speed grades are 250, 200, and 166 MHz
operations with no wait states. The
Internally self-timed output buffer control to eliminate the need
CY7C1354CV25/CY7C1356CV25 are equipped with the
to use asynchronous OE
advanced (NoBL) logic required to enable consecutive
read/write operations with data being transferred on every clock
Fully registered (inputs and outputs) for pipelined operation
cycle. This feature dramatically improves the throughput of data
Byte write capability in systems that require frequent write/read transitions. The
CY7C1354CV25/CY7C1356CV25 are pin-compatible with and
Single 2.5 V power supply (V )
DD
functionally equivalent to ZBT devices.
Fast clock-to-output times
All synchronous inputs pass through input registers controlled by
2.8 ns (for 250-MHz device) the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
Clock enable (CEN) pin to suspend operation
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
Synchronous self-timed writes
cycle.
Available in Pb-free 100-pin TQFP package, Pb-free and
Write operations are controlled by the byte write selects
nonPb-free 119-ball BGA package and 165-ball FBGA
(BW BW for CY7C1354CV25 and BW BW for
a d a b
package
CY7C1356CV25) and a write enable (WE) input. All writes are
IEEE 1149.1 JTAG-compatible boundary scan
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE , CE , CE ) and an
Burst capabilitylinear or interleaved burst order
1 2 3
asynchronous output enable (OE) provide for easy bank
ZZ sleep mode option and stop clock option
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated during
the data portion of a write sequence.
For a complete list of related documentation, click here.
Note
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 38-05537 Rev. *P Revised October 19, 2015CY7C1354CV25
CY7C1356CV25
Logic Block Diagram CY7C1354CV25
ADDRESS
A0, A1, A
REGISTER 0
A1 A1'
D1 Q1
A0 BURST A0'
D0 Q0
MODE LOGIC
ADV/LD
CLK C
C
CEN
WRITE ADDRESS WRITE ADDRESS
REGISTER 1 REGISTER 2
O
O
S
U
D U
E T
A T
P
N P
U T
U
S T
ADV/LD A
T
E
WRITE REGISTRY
R
MEMORY
AND DATA COHERENCY S B
BWa WRITE E DQs
ARRAY
CONTROL LOGIC G U
DRIVERS T DQPa
BWb A
I F
BWc E DQPb
M S
F
BWd
T E DQPc
P E
E R DQPd
R
WE S R
I S
S
E N E
G
INPUT INPUT
E E
REGISTER 1 REGISTER 0
OE
READ LOGIC
CE1
CE2
CE3
SLEEP
ZZ
CONTROL
Document Number: 38-05537 Rev. *P Page 2 of 34