CY7C1364CV33 9-Mbit (256 K 32) Pipelined Sync SRAM 9-Mbit (256 K 32) Pipelined Sync SRAM Features Functional Description Registered inputs and outputs for pipelined operation The CY7C1364CV33 SRAM integrates 256 K 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit 256 K 32 common I/O architecture counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock 3.3 V core power supply (V ) DD Input (CLK). The synchronous inputs include all addresses, all 2.5 V/3.3 V I/O power supply (V ) DDQ data inputs, address-pipelining Chip Enable (CE ), 1 depth-expansion Chip Enables (CE and CE ), Burst Control 2 3 Fast clock-to-output times inputs (ADSC, ADSP, and ADV), Write Enables (BW , and A:D 3.5 ns (for 166-MHz device) BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Provide high-performance 3-1-1-1 access rate Addresses and chip enables are registered at rising edge of User-selectable burst counter supporting Intel Pentium clock when either Address Strobe Processor (ADSP) or Address interleaved or linear burst sequences Strobe Controller (ADSC) are active. Subsequent burst Separate processor and controller address strobes addresses can be internally generated as controlled by the Advance pin (ADV). Synchronous self-timed writes Address, data inputs, and write controls are registered on-chip Asynchronous output enable to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further Available in JEDEC-standard lead-free 100-pin TQFP package details). Write cycles can be one to four bytes wide as controlled TQFP Available with 3-Chip Enable by the Byte Write control inputs. GW when active LOW causes all bytes to be written. ZZ Sleep Mode Option The CY7C1364CV33 operates from a +3.3 V core power supply while all outputs may operate with either a +2.5 or +3.3 V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. For a complete list of related documentation, click here. Selection Guide Description 166 MHz Unit Maximum Access Time 3.5 ns Maximum Operating Current 180 mA Maximum CMOS Standby Current 40 mA Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-74576 Rev. *C Revised November 20, 2014CY7C1364CV33 Logic Block Diagram CY7C1364CV33 A0, A1, A ADDRESS REGISTER 2 A 1:0 MODE Q1 ADV CLK BURST COUNTER CLR AND Q0 LOGIC ADSC ADSP DQD DQD BYTE BYTE BWD WRITE REGISTER WRITE DRIVER DQC DQC BYTE BWC BYTE OUTPUT WRITE DRIVER WRITE REGISTER OUTPUT MEMORY SENSE DQs BUFFERS ARRAY REGISTERS AMPS DQB E DQB BYTE BYTE BWB WRITE DRIVER WRITE REGISTER DQA DQA BYTE BWA BYTE WRITE DRIVER WRITE REGISTER BWE INPUT GW REGISTERS ENABLE PIPELINED CE1 REGISTER ENABLE CE2 CE3 OE SLEEP ZZ CONTROL Document Number: 001-74576 Rev. *C Page 2 of 21