Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY7C1366C CY7C1367C 9-Mbit (256K 36/512K 18) Pipelined DCD Sync SRAM 9-Mbit (256K 36/512K 18) Pipelined DCD Sync SRAM circuitry and a two-bit counter for internal burst operation. All Features synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous Supports bus operation up to 166 MHz inputs include all addresses, all data inputs, address-pipelining Available speed grade is 166 MHz chip enable (CE ), depth-expansion chip enables (CE and 1 2 1 CE ), burst control inputs (ADSC, ADSP, ADV), write and 3 Registered inputs and outputs for pipelined operation enables (BW , and BWE), and global write (GW). Asynchronous X Optimal for performance (double-cycle deselect) inputs include the output enable (OE) and the ZZ pin. Depth expansion without wait state Addresses and chip enables are registered at rising edge of 3.3 V 5% and + 10% core power supply (V ) DD clock when either address strobe processor (ADSP) or address 2.5 V/3.3 V I/O power supply (V ) strobe controller (ADSC) are active. Subsequent burst DDQ addresses can be internally generated as controlled by the Fast clock-to-output times advance pin (ADV). 3.5 ns (for 166 MHz device) Address, data inputs, and write controls are registered on-chip Provide high performance 3-1-1-1 access rate to initiate a self-timed write cycle.This part supports byte write operations (see Pin Definitions on page 6 and Partial Truth Table User-selectable burst counter supporting Intel Pentium for Read/Write on page 9 for further details). Write cycles can be interleaved or linear burst sequences one to four bytes wide as controlled by the byte write control Separate processor and controller address strobes inputs. GW This active LOW causes all bytes to be written. device incorporates an additional pipelined enable register which Synchronous self-timed writes delays turning off the output buffers an additional cycle when a deselect is executed. This feature enables depth expansion Asynchronous output enable without penalizing system performance. Available in Pb-free 100-pin TQFP and non Pb-free 119-ball The CY7C1366C/CY7C1367C operates from a +3.3 V core BGA package power supply while all outputs operate with a +3.3 V or a +2.5 V IEEE 1149.1 JTAG-compatible boundary scan supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. ZZ sleep mode option For a complete list of related documentation, click here. Functional Description The CY7C1366C/CY7C1367C SRAM integrates 256K 36 and 512K 18 SRAM cells with advanced synchronous peripheral Selection Guide Description 166 MHz Unit Maximum access time 3.5 ns Maximum operating current 180 mA Maximum CMOS standby current 40 mA Note 1. CE is for 100-pin TQFP. 119-ball BGA is offered only in 2 Chip Enable. 3 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05542 Rev. *O Revised March 28, 2019