CY7C1370D CY7C1372D 18-Mbit (512 K 36/1 M 18) Pipelined SRAM with NoBL Architecture 18-Mbit (512 K 36/1 M 18) Pipelined SRAM with NoBL Architecture Features Functional Description The CY7C1370D and CY7C1372D are 3.3 V, 512 K 36 and Pin-compatible and functionally equivalent to ZBT 1M18 synchronous pipelined burst SRAMs with No Bus Supports 250-MHz bus operations with zero wait states Latency (NoBL logic, respectively. They are designed to support unlimited true back-to-back read/write operations with Available speed grades are 250, 200, and 167 MHz no wait states. The CY7C1370D and CY7C1372D are equipped Internally self-timed output buffer control to eliminate the need with the advanced (NoBL) logic required to enable consecutive to use asynchronous OE read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data Fully registered (inputs and outputs) for pipelined operation in systems that require frequent write/read transitions. The Byte write capability CY7C1370D and CY7C1372D are pin compatible and functionally equivalent to ZBT devices. 3.3 V core power supply (V ) DD All synchronous inputs pass through input registers controlled by 3.3 V/2.5 V I/O power supply (V ) DDQ the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock Fast clock-to-output times input is qualified by the clock enable (CEN) signal, which when 2.6 ns (for 250 MHz device) deasserted suspends operation and extends the previous clock Clock enable (CEN) pin to suspend operation cycle. Write operations are controlled by the byte write selects Synchronous self-timed writes (BW BW for CY7C1370D and BW BW for CY7C1372D) a d a b Available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and a write enable (WE) input. All writes are conducted with and non Pb-free 65-ball FBGA package on-chip synchronous self-timed write circuitry. IEEE 1149.1 JTAG-compatible boundary scan Three synchronous chip enables (CE , CE , CE ) and an 1 2 3 asynchronous output enable (OE) provide for easy bank Burst capability linear or interleaved burst order selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tristated during ZZ sleep mode option and stop clock option the data portion of a write sequence. For a complete list of related documentation, click here. Selection Guide Description 250 MHz 200 MHz 167 MHz Unit Maximum access time 2.6 3.0 3.4 ns Maximum operating current 350 300 275 mA Maximum CMOS standby current 70 70 70 mA Errata: For information on silicon errata, see Errata on page 30. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05555 Rev. *S Revised November 17, 2014CY7C1370D CY7C1372D Logic Block Diagram CY7C1370D ADDRESS A0, A1, A REGISTER 0 A1 A1 D1 Q1 A0 BURST A0 D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O S U D U E T A T P N P U T U S T ADV/LD A T WRITE REGISTRY E R MEMORY AND DATA COHERENCY E S B BW a WRITE DQ s ARRAY CONTROL LOGIC G U DRIVERS T DQ Pa A BW b I F E DQ Pb BW c M S F BW d E DQ Pc T E P E R R DQ Pd S WE R I S S E N E G INPUT INPUT REGISTER 1 E REGISTER 0 E OE READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Logic Block Diagram CY7C1372D ADDRESS A0, A1, A REGISTER 0 A1 A1 D1 Q1 A0 BURST A0 D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O U U T T P S P D U E A U ADV/LD T N T T WRITE REGISTRY S A R MEMORY E B AND DATA COHERENCY WRITE DQ s BW a E ARRAY S U CONTROL LOGIC G DRIVERS A F T DQ Pa I M E F BW b S DQ Pb P E E T S R R E I S R N WE S G E E INPUT INPUT E E REGISTER 1 REGISTER 0 OE READ LOGIC CE1 CE2 CE3 Sleep ZZ Control Document Number: 38-05555 Rev. *S Page 2 of 35