THIS SPEC IS OBSOLETE Spec No: 38-05558 Spec Title: CY7C1370DV25/CY7C1372DV25, 18-MBIT (512K X 36/1M X 18) PIPELINED SRAM WITH NOBL(TM) ARCHITECTURE Replaced by: NONECY7C1370DV25 CY7C1372DV25 18-Mbit (512K 36/1M 18) Pipelined SRAM with NoBL Architecture 18-Mbit (512K 36/1M 18) Pipelined SRAM with NoBL Architecture Features Functional Description The CY7C1370DV25 and CY7C1372DV25 are 2.5 V, 512K 36 Pin-compatible and functionally equivalent to ZBT and 1M 18 synchronous pipelined burst SRAMs with No Bus Supports 200-MHz bus operations with zero wait states Latency (NoBL logic, respectively. They are designed to support unlimited true back-to-back read/write operations with Available speed grades are 200 and 167 MHz no wait states. The CY7C1370DV25 and CY7C1372DV25 are Internally self-timed output buffer control to eliminate the need equipped with the advanced NoBL logic required to enable to use asynchronous OE consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the Fully registered (inputs and outputs) for pipelined operation throughput of data in systems that require frequent write/read Byte write capability transitions. The CY7C1370DV25 and CY7C1372DV25 are pin-compatible and functionally equivalent to ZBT devices. Single 2.5 V core power supply (V ) DD All synchronous inputs pass through input registers controlled by 2.5 V I/O power supply (V ) DDQ the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock Fast clock-to-output times input is qualified by the clock enable (CEN) signal, which when 3.0 ns (for 200-MHz device) deasserted suspends operation and extends the previous clock Clock enable (CEN) pin to suspend operation cycle. Write operations are controlled by the byte write selects Synchronous self-timed writes (BW BW for CY7C1370DV25 and BW BW for a d a b Available in JEDEC-standard Pb-free 100-pin TQFP, and non CY7C1372DV25) and a write enable (WE) input. All writes are Pb-free 165-ball FBGA packages conducted with on-chip synchronous self-timed write circuitry. IEEE 1149.1 JTAG-compatible boundary scan Three synchronous chip enables (CE , CE , CE ) and an 1 2 3 asynchronous output enable (OE) provide for easy bank Burst capability linear or interleaved burst order selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated ZZ sleep mode option and stop clock option during the data portion of a write sequence. For a complete list of related documentation, click here. Selection Guide Description 200 MHz 167 MHz Unit Maximum access time 3.0 3.4 ns Maximum operating current 300 275 mA Maximum CMOS standby current 70 70 mA Errata: For information on silicon errata, see Errata on page 30. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05558 Rev. *P Revised November 3, 2016