CY7C1370KV25 CY7C1372KV25 18-Mbit (512K 36/1M 18) Pipelined SRAM with NoBL Architecture 18-Mbit (512K 36/1M 18) Pipelined SRAM with NoBL Architecture Latency (NoBL) logic, respectively. They are designed to Features support unlimited true back-to-back read/write operations with Pin-compatible and functionally equivalent to ZBT no wait states. The CY7C1370KV25 and CY7C1372KV25 are equipped with the advanced NoBL logic required to enable Supports 200-MHz bus operations with zero wait states consecutive read/write operations with data being transferred on Available speed grades are 200 and 167 MHz every clock cycle. This feature dramatically improves the Internally self-timed output buffer control to eliminate the need throughput of data in systems that require frequent write/read to use asynchronous OE transitions. The CY7C1370KV25 and CY7C1372KV25 are pin-compatible and functionally equivalent to ZBT devices. Fully registered (inputs and outputs) for pipelined operation All synchronous inputs pass through input registers controlled by Byte write capability the rising edge of the clock. All data outputs pass through output Single 2.5 V core power supply (V ) DD registers controlled by the rising edge of the clock. The clock input is qualified by the clock enable (CEN) signal, which when 2.5 V I/O power supply (V ) DDQ deasserted suspends operation and extends the previous clock Fast clock-to-output times cycle. 3.2 ns (for 200-MHz device) Write operations are controlled by the byte write selects Clock enable (CEN) pin to suspend operation (BW BW for CY7C1370KV25 and BW BW for a d a b CY7C1372KV25) and a write enable (WE) input. All writes are Synchronous self-timed writes conducted with on-chip synchronous self-timed write circuitry. Available in JEDEC-standard Pb-free 100-pin TQFP, and non Three synchronous chip enables (CE , CE , CE ) and an Pb-free 165-ball FBGA packages 1 2 3 asynchronous output enable (OE) provide for easy bank IEEE 1149.1 JTAG-compatible boundary scan selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated Burst capability linear or interleaved burst order during the data portion of a write sequence. ZZ sleep mode option and stop clock option Functional Description The CY7C1370KV25 and CY7C1372KV25 are 2.5 V, 512K 36 and 1M 18 synchronous pipelined burst SRAMs with No Bus Selection Guide Description 200 MHz 167 MHz Unit Maximum access time 3.0 3.4 ns 18 158 143 Maximum operating current mA 36 178 163 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-97851 Rev. *G Revised March 3, 2017CY7C1370KV25 CY7C1372KV25 Logic Block Diagram CY7C1370KV25 ADDRESS A0, A1, A REGISTER 0 A1 A1 D1 Q1 A0 BURST A0 D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O S U D U T E T A P N P U T U T ADV/LD S A T WRITE REGISTRY E R MEMORY AND DATA COHERENCY B BWa WRITE E S DQs ARRAY CONTROL LOGIC G U DRIVERS T DQPa A BWb I F BWc E DQPb M S F BWd T E DQPc E P E R DQPd R S WE R S I S E N E G INPUT INPUT E E REGISTER 1 REGISTER 0 OE READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Logic Block Diagram CY7C1372KV25 ADDRESS A0, A1, A REGISTER 0 A1 A1 D1 Q1 A0 A0 BURST D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O U U T T P S P D U E U ADV/LD A T N T T WRITE REGISTRY S A R MEMORY E B AND DATA COHERENCY BWa WRITE E DQs ARRAY S U CONTROL LOGIC G DRIVERS A F T DQPa I M F E BWb S DQPb P E E T S R R E S I R N WE S G E E INPUT INPUT REGISTER 1 E REGISTER 0 E OE READ LOGIC CE1 CE2 CE3 Sleep ZZ Control Document Number: 001-97851 Rev. *G Page 2 of 30