CY7C1370KV33/CY7C1370KVE33 CY7C1372KV33/CY7C1372KVE33 18-Mbit (512K 36/1M 18) Pipelined SRAM with NoBL Architecture (With ECC) 18-Mbit (512K 36/1M 18) Pipelined SRAM with NoBL Architecture (With ECC) Features Functional Description The CY7C1370KV33/CY7C1370KVE33/CY7C1372KV33/ Pin-compatible and functionally equivalent to ZBT CY7C1372KVE33 are 3.3 V, 512K36 and 1M18 Supports 250-MHz bus operations with zero wait states synchronous pipelined burst SRAMs with No Bus Latency (NoBL logic, respectively. They are designed to support Available speed grades are 250, 200, and 167 MHz unlimited true back-to-back read/write operations with no wait Internally self-timed output buffer control to eliminate the need states. The CY7C1370KV33/CY7C1370KVE33/ to use asynchronous OE CY7C1372KV33/CY7C1372KVE33 are equipped with the advanced (NoBL) logic required to enable consecutive Fully registered (inputs and outputs) for pipelined operation read/write operations with data being transferred on every clock Byte write capability cycle. This feature dramatically improves the throughput of data in systems that require frequent write/read transitions. The 3.3 V core power supply (V ) DD CY7C1370KV33/CY7C1370KVE33/CY7C1372KV33/ CY7C1372KVE33 are pin compatible and functionally equivalent 3.3 V/2.5 V I/O power supply (V ) DDQ to ZBT devices. Fast clock-to-output times All synchronous inputs pass through input registers controlled by 2.5 ns (for 250 MHz device) the rising edge of the clock. All data outputs pass through output Clock enable (CEN) pin to suspend operation registers controlled by the rising edge of the clock. The clock input is qualified by the clock enable (CEN) signal, which when Synchronous self-timed writes deasserted suspends operation and extends the previous clock cycle. Available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free 165-ball FBGA package Write operations are controlled by the byte write selects (BW a BW for CY7C1370KV33/CY7C1370KVE33 and BW BW for d a b IEEE 1149.1 JTAG-compatible boundary scan CY7C1372KV33/CY7C1372KVE33) and a write enable (WE) Burst capability linear or interleaved burst order input. All writes are conducted with on-chip synchronous self-timed write circuitry. ZZ sleep mode option and stop clock option Three synchronous chip enables (CE , CE , CE ) and an 1 2 3 On chip Error Correction Code (ECC) to reduce Soft Error Rate asynchronous output enable (OE) provide for easy bank (SER) selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tristated during the data portion of a write sequence. Selection Guide Description 250 MHz 200 MHz 167 MHz Unit Maximum access time 2.5 3.0 3.4 ns Maximum operating current 18 180 158 143 mA 36 200 178 163 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-97836 Rev. *H Revised May 19, 2017CY7C1370KV33/CY7C1370KVE33 CY7C1372KV33/CY7C1372KVE33 Logic Block Diagram CY7C1370KV33 ADDRESS A0, A1, A REGISTER 0 A1 A1 D1 Q1 A0 BURST A0 D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O S U D U E T A T P N P U T U S T ADV/LD A T WRITE REGISTRY E R MEMORY AND DATA COHERENCY E S B BW a WRITE DQ s ARRAY CONTROL LOGIC G U DRIVERS T DQ Pa A BW b I F E DQ Pb BW c M S F BW d E DQ Pc T E P E R R DQ Pd S WE R I S S E N E G INPUT INPUT REGISTER 1 E REGISTER 0 E OE READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Logic Block Diagram CY7C1370KVE33 ADDRESS A0, A1, A REGISTER 0 A1 A1 D1 Q1 A0 BURST A0 D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O S U D E U T E T A C P N P U T C U T ADV/LD S A T E WRITE REGISTRY D R MEMORY AND DATA COHERENCY E S E B DQs BWA WRITE ARRAY CONTROL LOGIC G U DRIVERS T C BWB A DQPA I F E O DQPB BWC M S F E D T DQPC BWD P E E R E R DQPD S WE R S I R S E N E G ECC INPUT INPUT ENCODER REGISTER 1 E REGISTER 0 E OE READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Document Number: 001-97836 Rev. *H Page 2 of 32